View ZL50404_377996.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ZL50404 Lightly Managed/Unmanaged 5-Port 10/100M Ethernet Switch
Data Sheet Features
* * * * * * * * * 4 10/100 Mbps auto-negotiating ports with RMII, MII & GPSI interface options 1 10/100 Mbps auto-negotiating MII port (port 9) that can be used as a WAN uplink or as a 5th port Serial interface for configuration in unmanaged mode or light management mode Internal 2Mbit (256KB) buffer memory Up to 4K MAC addresses Provides port based VLAN support 8 port trunking groups with up to 4 ports per group Failover Backplane Features * Link Heart Beat Rate Control (both ingress and egress) * Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement) * Smooth out traffic to uplink ports * Ingress Rate Control - Back pressure - Flow control - WRED (Weighted Random Early Discard) Ordering Information ZL50404GDC 208 Pin LBGA
July 2003
-40C to +85C Egress Rate Control - per queue shaper (Port 9) - WRED * Down to 16kbps Rate Control granularity Packet Filtering and Port Security * Static address filtering for source and/or destination MAC * Static MAC address not subject to aging * Secure mode freezes MAC address learning (each port may independently use this mode) Full Duplex Ethernet IEEE 802.3x Flow Control Backpressure flow control for Half Duplex ports *
*
* *
C P U
Serial
ZL50404 Lightly Managed/ Unmanaged 5-Port 10/100M Ethernet Switch
MII
10/100 PHY
EEPROM
I2C
RMII / MII / GPSI
Quad 10/100 PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 7/8/03, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50404
* * *
Data Sheet
*
* * * * * * *
Supports Ethernet multicasting and broadcasting and flooding control Supports per-system option to enable flow control for best effort frames even on QoS enabled ports QoS Support * Supports IEEE 802.1p/Q Quality of Service with 2 transmission priority queues (4 for MII port), with strict priority and WFQ service disciplines * Provides 2 levels of dropping precedence with WRED mechanism * User controls the WRED thresholds. * Buffer management: per class and per port buffer reservations * Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID Classification based on: * Port based priority * VLAN Priority field in VLAN tagged frame * DS/TOS field in IP packet * UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range The precedence of the above classifications is programmable MIB Statistics counters for all ports Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports I2C EEPROM for configuration in unmanaged mode Built-in reset logic triggered by system malfunction Built-In Self Test for internal SRAM IEEE-1149.1 (JTAG) test port
Description
The ZL50404 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 5 ports at 10/100 Mbps and a CPU interface for lightly managed and unmanaged switch applications. The chip supports up to 4K MAC addresses and port-based Virtual LANs (VLANs). With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50404 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission priorities (4 priorities for MII port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The ZL50404 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The ZL50404 supports 8 groups of port trunking/load sharing. Each group can contain up to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50404 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports. Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network management solution. The ZL50404 is fabricated using 0.18 micron technology. The ZL50404 is packaged in a 208-pin Ball Grid Array package.
2
Zarlink Semiconductor Inc.
ZL50404 Table of Contents
Data Sheet
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Power and Ground Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 Ball Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 Signal Mapping in different operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 Bootstrap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 MII MAC Module (MMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 RMII MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Light Management Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 Other Internal Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8 Light Management and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.9 Register Configuration, Frame Transmission, and Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9.1 Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9.2 Rx/Tx of Standard Ethernet Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.9.3 Control Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.10 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.10.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.10.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.10.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.10.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.10.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.10.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.11 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.11.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.11.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.12 Timeout Reset Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.13 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.0 ZL50404 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 MAC Address Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.8 Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.9 Port Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
5.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 Frame Engine Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.1 FCB Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.3 RxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.5 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.6 TxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 Two QoS Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.1 Strict Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.2 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4 Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.5 Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.6 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.6.1 Dropping When Buffers Are Scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7 ZL50404 Flow Control Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.8 Mapping to IETF Diffserv Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.9 Failover Backplane Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.0 Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.1 Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2 Using port mirroring for loop back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.0 GPSI (7WS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 GPSI connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.0 Clock Speed Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.1 System Clock (SCLK) speed requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.2 RMAC Reference Clock (M_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.3 MMAC Reference Clock (REF_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.0 Hardware Statistics Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.2 IEEE 802.3 HUB Management (RFC 1516) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2.1.3 FCSERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2.1.5 FrameTooLongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2.1.6 ShortEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2.1.7 Runts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2.1.8 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2.1.9 LateEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.2.1.10 VeryLongEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.2.1.11 DataRateMisatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.2.1.12 AutoPartitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.2.1.13 TotalErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
11.3 IEEE - 802.1 Bridge Management (RFC 1286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.3.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.3.1.1 InFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.3.1.2 OutFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.3.1.3 InDiscards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.3.1.4 DelayExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.3.1.5 MtuExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.4 RMON - Ethernet Statistic Group (RFC 1757) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.4.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.4.1.1 Drop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.4.1.2 Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.4.1.3 BroadcastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.4.1.4 MulticastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.4.1.5 CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.4.1.6 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.4.1.7 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.4.1.8 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.4.1.9 Jabbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.4.1.10 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.4.1.11 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.1 ZL50404 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2.1 INDEX_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2.2 INDEX_REG1 (only needed for 8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2.3 DATA_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2.4 CONTROL_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2.5 COMMAND&STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2.6 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.2.7 Control Command Frame Buffer1 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.2.8 Control Command Frame Buffer2 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3 Indirectly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3.1 (Group 0 Address) MAC Ports Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3.1.1 ECR1Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3.1.2 ECR2Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.3.1.3 ECR3Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.3.1.4 ECR4Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.3.1.5 BUF_LIMIT - Frame Buffer Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3.1.6 FCC - Flow Control Grant Period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3.2 (Group 1 Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3.2.1 AVTCL - VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3.2.2 AVTCH - VLAN Type Code Register High. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3.2.3 PVMAP00_0 - Port 0 Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3.2.4 PVMAP00_1 - Port 0 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3.2.5 PVMAP00_3 - Port 0 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3.2.6 PVMAPnn_0,1,3 - Ports 1~3,8,9 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3.2.7 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3.3 (Group 2 Address) Port Trunking Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.3.3.1 TRUNKn- Trunk Group 0~7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.3.3.2 TRUNKn_HASH10 - Trunk group 0~7 hash result 1/0 destination port number . . . . . . . . . 60 12.3.3.3 TRUNKn_HASH32 - Trunk group 0~7 hash result 3/2 destination port number . . . . . . . . . 60 12.3.3.4 TRUNKn_HASH54 - Trunk group 0~7 hash result 5/4 destination port number . . . . . . . . . 60 12.3.3.5 TRUNKn_HASH76 - Trunk group 0~7 hash result 7/6 destination port number . . . . . . . . . 60
5
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
Multicast Hash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.3.3.6 MULTICAST_HASHn-0 - Multicast hash result 0~7 mask byte 0 . . . . . . . . . . . . . . . . . . . . 61 12.3.3.7 MULTICAST_HASHn-1 - Multicast hash result 0~7 mask byte 1 . . . . . . . . . . . . . . . . . . . . 61 12.3.4 (Group 3 Address) CPU Port Configuration Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.3.4.1 MAC0 - CPU Mac address byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.3.4.2 MAC1 - CPU Mac address byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.3.4.3 MAC2 - CPU Mac address byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.3.4.4 MAC3 - CPU Mac address byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.3.4.5 MAC4 - CPU Mac address byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.3.4.6 MAC5 - CPU Mac address byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.3.4.7 INT_MASK0 - Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.3.4.8 INTP_MASK0 - Interrupt Mask for MAC Port 0,1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.3.4.9 INTP_MASKn - Interrupt Mask for MAC Ports Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.3.4.10 RQS - Receive Queue Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.3.4.11 RQSS - Receive Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.3.4.12 MAC01 - Increment MAC port 0,1 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.3.4.13 MAC23 - Increment MAC port 2,3 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3.4.14 MAC9 -Increment MAC port 9 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3.5 (Group 4 Address) Search Engine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3.5.1 AGETIME_LOW - MAC address aging time Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3.5.2 AGETIME_HIGH -MAC address aging time High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3.5.3 SE_OPMODE - Search Engine Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.3.6 (Group 5 Address) Buffer Control/QOS Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.3.6.1 QOSC - QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.3.6.2 UCC - Unicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.3.6.3 MCC - Multicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.3.6.4 MCCTH - Multicast Threshold Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.3.6.5 RDRC0 - WRED Rate Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.3.6.6 RDRC1 - WRED Rate Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.3.6.7 RDRC2 - WRED Rate Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.3.6.8 SFCB - Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.3.6.9 C1RS - Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.3.6.10 C2RS - Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.3.6.11 C3RS - Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.3.6.12 AVPML - VLAN Tag Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.3.6.13 AVPMM - VLAN Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.3.6.14 AVPMH - VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.3.6.15 AVDM - VLAN Discard Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.3.6.16 TOSPML - TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.3.6.17 TOSPMM - TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.3.6.18 TOSPMH - TOS Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.3.6.19 TOSDML - TOS Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.3.6.20 USER_PROTOCOL_[7:0] - User Define Protocol 0~7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.6.21 USER_PROTOCOL_FORCE_DISCARD[7:0] - User Define Protocol 0~7 Force Discard 72 User Defined Logical Ports and Well Known Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.3.6.22 WELL_KNOWN_PORT[1:0]_PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . . . 73 12.3.6.23 WELL_KNOWN_PORT[3:2]_PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . . . 73 12.3.6.24 WELL_KNOWN_PORT[5:4]_PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . . . 74 12.3.6.25 WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority . . . . . . 74 12.3.6.26 WELL_KNOWN_PORT_ENABLE[7:0] - Well Known Logic Port 0 to 7 Enables. . . . . . . . 74 12.3.6.27 WELL_KNOWN_PORT_FORCE_DISCARD[7:0] - Well Known Logic Port 0~7 Force Discard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.3.6.28 USER_PORT[7:0]_[LOW/HIGH] - User Define Logical Port 0~7 . . . . . . . . . . . . . . . . . . . 75 12.3.6.29 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority . . . . . . . . . . . . . 75
6
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
12.3.6.30 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority . . . . . . . . . . . . . 75 12.3.6.31 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority . . . . . . . . . . . . . 76 12.3.6.32 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority . . . . . . . . . . . . . 76 12.3.6.33 USER_PORT_ENABLE[7:0] - User Define Logic Port 0 to 7 Enables . . . . . . . . . . . . . . . 76 12.3.6.34 USER_PORT_FORCE_DISCARD[7:0] - User Define Logic Port 0~7 Force Discard . . . . 76 12.3.6.35 RLOWL - User Define Range Low Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.6.36 RLOWH - User Define Range Low Bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.6.37 RHIGHL - User Define Range High Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.6.38 RHIGHH - User Define Range High Bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.6.39 RPRIORITY - User Define Range Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.7 (Group 6 Address) MISC Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.7.1 MII_OP0 - MII Register Option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.7.2 MII_OP1 - MII Register Option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.7.3 FEN - Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.7.4 MIIC0 - MII Command Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.3.7.5 MIIC1 - MII Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.3.7.6 MIIC2 - MII Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.7.7 MIIC3 - MII Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.7.8 MIID0 - MII Data Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.7.9 MIID1 - MII Data Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.7.10 USD - One Micro Second Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3.7.11 DEVICE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3.7.12 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3.7.13 LHBTimer - Link Heart Beat Timeout Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.7.14 LHBReg0, LHBReg1 - Link Heart Beat OpCode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.7.15 fMACCReg0, fMACCReg1 - MAC Control Frame OpCode . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.7.16 FCB Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.7.17 FCB Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.7.18 FCB Base Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.8 (Group 7 Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.3.8.1 MIRROR CONTROL - Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.3.8.2 MIRROR_DEST_MAC[5:0] - Mirror Destination Mac Address 0~5 . . . . . . . . . . . . . . . . . . . 83 12.3.8.3 MIRROR_SRC _MAC[5:0] - Mirror Destination Mac Address 0~5 . . . . . . . . . . . . . . . . . . . 83 12.3.8.4 RMAC_MIRROR0 - RMAC Mirror 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.3.8.5 RMAC_MIRROR1 - RMAC Mirror 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.9 (Group 8 Address) Per Port QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.9.1 FCRn - Port 0~3,8,9 Flooding Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.9.2 BMRCn - Port 0~3,8,9 Broadcast/Multicast Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.9.3 PR100_n - Port 0~3 Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.9.4 PR100_CPU - Port CPU Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.9.5 PRM - Port MMAC Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.9.6 PTH100_n - Port 0~3 Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.9.7 PTH100_CPU - Port CPU Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.9.8 PTHM - Port MMAC Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.9.9 QOSC00, QOSC01 - Classes Byte Limit port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.9.10 QOSC02, QOSC07 - Classes Byte Limit port 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.9.11 QOSC16 - QOSC21 - Classes Byte Limit CPU port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.9.12 QOSC22 - QOSC27 - Classes Byte Limit MMAC port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.9.13 QOSC28 - QOSC31 - Classes WFQ Credit For MMAC. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.9.14 QOSC36 - QOSC39 - Shaper Control Port MMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.10 (Group E Address) System Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.10.1 DTSRL - Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.10.2 DTSRM - Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.10.3 TESTOUT0, TESTOUT1 - Testmux Output [7:0], [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
12.3.10.4 MASK0-MASK4 - Timeout Reset Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.3.10.5 BOOTSTRAP0 - BOOTSTRAP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.3.10.6 PRTFSMST[9,8,3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.3.10.7 PRTQOSST0-PRTQOSST3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.3.10.8 PRTQOSST8A, PRTQOSST8B (CPU port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.3.10.9 PRTQOSST9A, PRTQOSST9B (MMAC port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.3.10.10 CLASSQOSST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.3.10.11 PRTINTCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.3.10.12 QMCTRL[9,8,3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.3.10.13 QCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.3.10.14 BMBISTR0, BMBISTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.3.10.15 BMControl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.3.10.16 BUFF_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.3.10.17 FCB_HEAD_PTR0, FCB_HEAD_PTR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.3.10.18 FCB_TAIL_PTR0, FCB_TAIL_PTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.3.10.19 FCB_NUM0, FCB_NUM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.3.10.20 BM_RLSFF_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.3.10.21 BM_RSLFF_INFO[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.3.11 (Group F Address) CPU Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.3.11.1 GCR - Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.3.11.2 DCR - Device Status and Signature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.3.11.3 DCR1 - Device Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.3.11.4 DPST - Device Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.3.11.5 DTST - Data read back register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.11.6 DA - DA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 13.0 Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.3 Recommended Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.4 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.4.2 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.4.3 Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 13.4.4 General Purpose Serial Interface (7-wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.4.5 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.4.6 IC Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.4.7 Serial Interface Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.4.8 JTAG (IEEE 1149.1-2001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8
Zarlink Semiconductor Inc.
ZL50404
1.0
1.1
Data Sheet
BGA and Ball Signal Descriptions
BGA Views (Top-View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A
SCLK
DATAI N SDA
DATA OUT SCL
STRO BE RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
REF_ CLK TCK
RSVD
M9_M TXCK RSVD
M9_T XEN M9_R XCK M9_C OL
A
B
P_INT # RESE TOUT # RESI N# M2_C OL M_M DC M0_R XD0 M0_C RS M0_T XD0 M1_R XD0 M1_C RS M1_T XD0 M2_R XD3 M2_R XD2 M2_R XD1 M2_R XD0 1
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TMS
B
C
TSTO UT1
TSTO UT3
TSTO UT5
TSTO UT6
TSTO UT7
TSTO UT9
TSTO UT11
TSTO UT12
TSTO UT14
TSTO UT15
TRST #
TDI
RSVD
M9_C RS
C
D
TSTO UT0 M0_C OL M_M DIO M0_R XD1 M0_T XEN M0_T XD1 M1_R XD1 M1_T XEN M1_T XD1 M2_T XCK M2_R XCK M2_T XEN M2_C RS 2
TSTO UT2 M1_C OL M0_R XD2 M0_R XCK M0_T XD2 M0_T XCK M1_R XD2 M1_T XD2 M1_T XCK M2_T XD3 M2_T XD2 M2_T XD1 M2_T XD0 3
TSTO UT4 3.3V
3.3V
SCAN _EN
TSTO UT8
TSTO UT10
1.8V
TSTO UT13
TDO
3.3V
RSVD
RSVD
M9_R XDV RSVD
RSVD
D
E
3.3V
RSVD
RSVD
E
F
M0_R XD3 M0_T XD3 1.8V GND GND GND GND
M9_R XD2 M9_R XD0 1.8V
M9_R XD3 M9_R XD1 RSVD
RSVD
RSVD
F
G
M9_T XD2 M9_T XD0 RSVD
M9_T XD3 M9_T XD1 RSVD
G
H
GND
GND
GND
GND
H
J
M1_R XD3 M1_R XCK M1_T XD3 3.3V
GND
GND
GND
GND
RSVD
RSVD
J
K
GND
GND
GND
GND
RSVD
RSVD
RSVD
RSVD
K
L
RSVD
RSVD
RSVD
RSVD
L
M
3.3V
RSVD
RSVD
RSVD
M
N
M3_R XD3 M3_R XD2 M3_R XD1 M3_R XD0 4
3.3V
M3_T XD3 M3_T XD2 M3_T XD1 M3_T XD0 6
1.8V
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
N
P
M3_R XCK M3_T XEN M3_C RS 5
M3_C OL M_CL K M3_T XCK 7
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
P
R
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
R
T
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
T
8
9
10
11
12
13
14
15
16
1.2
Power and Ground Distribution
GND
G7-10, H7-10, J7-10, K7-10 D5, D12, E4, E13, M4, M13, N5 D9, H4, H13, N7
VSS VCC VDD
Ground I/O Power Core Power
3.3V 1.8V
9
Zarlink Semiconductor Inc.
ZL50404
1.3
Notes #= Input = In-ST = Output = Out-OD= I/O-TS = I/O-OD = Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Output signal with Open-Drain driver Input & Output signal with Tri-State driver Input & Output signal with Open-Drain driver
Data Sheet
Ball Signal Descriptions
All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive.
Ball Signal Description Table
Ball No(s)
2
Symbol SDA SCL STROBE DATAOUT DATAIN P_INT# M[3:0]_RXD[3:0]
I/O I/O with pull up Output Input with pull up Output with pull up Input with pull up Output Input with pull up
Description Serial Data Line Serial Clock Line Clock signal Data out Data in Interrupt Ports [3:0] - Receive Data Bit [3:0]
I C Interface (TSTOUT[3] bootstrap must be '1') B2 B3 Serial Interface A4 A3 A2 B1 L13, K14, L15, L16, N14, P14, R14, T14, N11, P11, R11, T11, N8, P8, R8, T8 K16, T15, T12, T9 K15, R15, R12, R9 J13, K13, J15, J16, N16, P16, R16, T16, N13, P13, R13, T13, N10, P10, R10, T10 H14, M14, M15, M16 J14, N15, N12, N9 L14, P15, P12, P9 G16, G15, H16, H15 D15 C15 C16 B16
Fast Ethernet Access Ports [3:0] MII
M[3:0]_CRS_DV M[3:0]_TXEN M[3:0]_TXD[3:0]
Input with pull up I/O-TS with slew Output, slew
Ports [3:0] - Carrier Sense and Receive Data Valid Ports [3:0] - Transmit Enable These pins also serve as bootstrap pins. Ports [3:0] - Transmit Data Bit [3:0]
M[3:0]_COL M[3:0]_TXCLK M[3:0]_RXCLK M9_TXD[3:0] M9_RXDV M9_CRS M9_COL M9_RXCLK
Input with pull down, I/O with pull up, I/O with pull up, Output Input w/ pull up Input w/ pull down Input w/ pull down I/O w/ pull up
Ports[3:0] - Collision Ports[3:0] - Transmit Clock Ports[3:0] - Receive Clock Transmit Data Bit [3:0] Receive Data Valid Carrier Sense Collision Detected Receive Clock
MII Ethernet Access Port
10
Zarlink Semiconductor Inc.
ZL50404
Ball Signal Description Table (continued)
Data Sheet
Ball No(s) F14, F13, G14, G13 A16 A15 A13 Test Interface D2, C2, D3, C3, D4, C4, C5, C6, D7, C7, D8, C8, C9, D10, C10, C11
Symbol M9_RXD[3:0] M9_TXEN M9_ MTXCLK REF_CLK TSTOUT[15:0]
I/O Input w/ pull up Output w/ pull up I/O w/ pull up Input w/ pull up I/O-TS
Description Receive Data Bit [3:0] Transmit Data Enable Transmit Clock MMAC Reference Clock [15:4] Reserved [3] EEPROM checksum is good [2] Initialization Completed [1] Memory Self Test in progress [0] Initialization started These pins also serve as bootstrap pins.
Test Facility C13 C12 B13 B14 D11 D6 TDI TRST# TCK TMS TDO SCAN_EN Input w/pull up Input w/pull up Input w/pull up Input w/pull up Output Input JTAG Test JTAG Test JTAG Test JTAG Test JTAG Test Scan Enable. Manufacturing test option. Should be externally pulled-down for proper operation System Clock. Based on system requirement, SCLK needs to operate at difference frequency. SCLK requires 40/60% duty cycle clock +1.8 Volt DC Supply +3.3 Volt DC Supply Ground
System Clock, Power, and Ground Pins A1 SCLK Input
D9, H4, H13, N7, D5, D12, E4, E13, M4, M13, N5, G7-10, H7-10, J7-10, K7-10
VDD VCC VSS
Power Power Power Ground
11
Zarlink Semiconductor Inc.
ZL50404
Ball Signal Description Table (continued)
Data Sheet
Ball No(s) MISC R9, R12, R15, K15, T10, R10, P10, N10, T13, R13, P13, N13, T16, R16, P16, N16, J16 J15, K13, J13, T9, T12, T15, K16, M16, M15, M14, H14, N9, N12, N15, J14, P9, P12, P15, L14, T8, R8, P8, N8, T11, R11, P11, N11, T14, R14, P14, N14, L16, L15, K14, L13, F15, F16, E15, E16, E14, D13, D14, C14, A14, B15, D16, B4, B5 , A5, B6, A6, B7, A7, B8, A8, B9, A9, B10, A10, B11, A11, B12 , A12 D1 C1 F1 F2 R7 D2
Symbol RSVD NC
I/O
Description Reserved Pins. Leave unconnected.
RESIN# RESETOUT# M_MDC M_MDIO M_CLK
1
Input Output Output I/O-TS with pull up Input I/O-TS
Reset Input Reset PHY MII Management Data Clock - MII Management Data I/O - RMAC Reference Clock Enable Debounce of STROBE signal Pullup - Enabled Pulldown - Disabled Reserved. Must be pulled-up.
Bootstrap Pins (1= pull up 0= pull down) TSTOUT[0]
D3, C2
TSTOUT[2:1]
I/O-TS Must be externally pulled-up
C3
TSTOUT[3]
I/O-TS
Management interface operation mode: 0 - Lightly Managed Serial. CPU can transmit/receive packet with the serial interface. 1 - Unmanaged Serial. No CPU packet can be transmit or received with the serial interface. EEPROM can be used to configure the device at bootup. A one (1) indicates pullup. A zero (0) indicates pulldown.
12
Zarlink Semiconductor Inc.
ZL50404
Ball Signal Description Table (continued)
Data Sheet
Ball No(s) C5, C4, D4
Symbol TSTOUT[6:4] I/O-TS
I/O
Description Device ID. Default address of the device for serial interface. Up to 8 device can be sharing the serial management bus with different device ID. A one (1) indicates pullup. A zero (0) indicates pulldown. TSTOUT[4] is the Least Significant Bit (LSB).
C6
TSTOUT7
I/O-TS
EEPROM not installed. Pullup: Not installed Pulldown: Installed Manufacturing Option. Must be pulled-up.
D7
TSTOUT8
I/O-TS Must be externally pulled-up
C7
TSTOUT9
I/O-TS
Module Detect Pullup: Enable. In this mode, the device will detect the existence of a PHY (for hot swap purpose). Pulldown: Disable
D8
TSTOUT10
I/O-TS Must be externally pulled-down
Reserved. Must be pulled-down.
C8
TSTOUT11
I/O-TS
Power Saving Pullup: Enable Mac power saving mode Pulldown: Disable Mac power saving mode Timeout Reset Enable Pullup: Enable Pulldown: Disable Manufacturing Options. Must be pulled-up.
C9
TSTOUT12
I/O-TS
D10
TSTOUT[15:13]
I/O-TS Must be externally pulled-up
K15, R15, R12, R9
M[3:0]_TXEN
I/O-TS Slew
User Defined Bootstrap: Usually used in conjuction with Module Detect to determine what interface to use for the inserted module. Can be read from BOOTSTRAP2 register
1. External pull-up/down resistors are required on all bootstrap pins for proper operation. Recommend 10K for pull-ups and 1K for pull-downs.
13
Zarlink Semiconductor Inc.
ZL50404
1.4 Signal Mapping in different operation mode
Data Sheet
The ZL50404 Fast Ethernet ports (0-3) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in Table , "Ball Signal Description Table" on page 10.
Notes: I - Input O - Output U - Pullup D - Pulldown
Fast Ethernet Ports Pin Symbol M[3:0]_RXD0 M[3:0]_RXD1 M[3:0]_RXD2 M[3:0]_RXD3 M[3:0]_TXEN M[3:0]_CRS_DV M[3:0]_TXD0 M[3:0]_TXD1 M[3:0]_TXD2 M[3:0]_TXD3 M[3:0]_COL M[3:0]_TXCLK M[3:0]_RXCLK
No Module (U) (U) (U) (U) (O) (U) (O) (O) (O) (O) (D) (U) (U)
RMII Mode
(ECR4Pn[4:3]='11')
MII Mode
(ECR4Pn[4:3]='01')
GPSI Mode
(ECR4Pn[4:3]='00')
M[3:0]_RXD0 (IU) M[3:0]_RXD1 (IU) NC NC M[3:0]_TXEN (O) M[3:0]_CRS_DV (IU) M[3:0]_TXD0 (O) M[3:0]_TXD1 (O) NC NC NC NC NC
M[3:0]_RXD0 (IU) M[3:0]_RXD1 (IU) M[3:0]_RXD2 (IU) M[3:0]_RXD3 (IU) M[3:0]_TXEN (O) M[3:0]_DV (IU) M[3:0]_TXD0 (O) M[3:0]_TXD1 (O) M[3:0]_TXD2 (O) M[3:0]_TXD3 (O) M[3:0]_COL (ID) M[3:0]_TXCLK (IOU) M[3:0]_RXCLK (IOU)
M[3:0]_RXD (IU) NC NC NC M[3:0]_TXEN (O) M[3:0]_CRS (IU) M[3:0]_TXD (O) NC NC NC M[3:0]_COL (ID) M[3:0]_TXCLK (IOU) M[3:0]_RXCLK (IOU)
Table 1 - Signal Mapping In Different Operation Mode
14
Zarlink Semiconductor Inc.
ZL50404
1.5 Bootstrap Options
Data Sheet
TSTOUT[15:0] and M[3:0]_TXEN pins serve as bootstrap pins during device power-up or reset. Please refer to "Typical Reset & Bootstrap Timing Diagram" on page 100 for more information on when the bootstrap pins are sampled. The bootstrap pins require external pull-up/down resistors for proper operation. The table below summarizes the bootstrap options. Feature CPU Interface Description The ZL50404 allows the selection of 2 different management interfaces: serial only and unmanaged serial with I2C EEPROM. TSTOUT[3] is used to select the interface options mentioned above. If the serial interface is selected, addition bootstrap options are required: * TSTOUT[0] enables or disables the DEBOUNCE feature (refer to "Synchronous Serial Interface" on page 21) * TSTOUT[6:4] selects the device ID Also, an optional I2C EEPROM can be used to configure the device at power-up or reset. TSTOUT[7] selects the EEPROM option. Ethernet Interface The ZL50404 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[3:0]_TXEN (ports 0-3) are used to specify the module type to support multiple ethernet interfaces during module hotswap. Another feature is the ZL50404 MAC power savings mode. When enabled via TSTOUT[11], each port's MAC will detect inactivity on the port and go into a power savings state. Once activitiy is detected once again on the port, the MAC will come out of this state. Misc. Features One other feature selected via bootstrap is Timeout Reset Enable (TSTOUT[12]). This enables a monitoring block with the device which will detect if any hardware state machine is in a non-idle state for more than 5 seconds. Refer to section 2.12 for more details on this feature. Table 2 - Bootstrap Features
15
Zarlink Semiconductor Inc.
ZL50404
2.0 Block Functionality
Data Sheet
MMAC
RMAC X 4
Frame Engine
Search Engine
Other Internal Memory Block
Management Module
Management Light Module
Internal Memory
Figure 2 - Functional Block Diagram
2.1
Internal Memory
Two Megabit of internal memory is provided for ethernet Frame Data Buffering (FDB) and for storing of Mac Control Table database (MCT). The MCT is used for storing MAC addresses and their physical port number. The FDB is used for storing the received frame data contents. The contents are stored in this memory until it is ready to be transmitted to the egress port. A memory arbiter is used to arbitrary the memory access requests from various sources. Build in self test is used to detect any error in the memory array when the device is powered up. Build in self test can also be requested by the writing the GCR register.
2.2
MII MAC Module (MMAC)
The MII Media Access Control (MMAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The ZL50404 MMAC implements the MII interface and meets the IEEE 802.3Z specification. It is able to operate in 10M/100M either Half or Full Duplex mode with a back pressure/flow control mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. This port is denoted as port 9. The PHY address for the PHY device connected to the MMAC port has to be 10h.
2.3
RMII MAC Module (RMAC)
The RMII Media Access Control (RMAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). It has three interfaces, MII, RMII or GPSI (only for 10M). The RMAC of the ZL50404 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for up to 16 total transmissions. These four ports are denoted as ports 0 to 3. The PHY addresses for the PHY devices connected to the 4 RMAC ports has to be from 08h (port 0) to 0Bh (port 3).
16
Zarlink Semiconductor Inc.
ZL50404
2.4 Light Management Module
Data Sheet
The CPU can send a control frame to access or configure the internal network management database. The Light Management Module decodes the control frame and executes the functions requested by the CPU. This Module is only active in lightly managed serial mode. In unmanaged serial mode, no control frame is accepted by the device.
2.5
Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the search engine, to resolve the destination port. The arriving frame is moved to the internal memory. After receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
2.6
Search Engine
The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2) by searching the database. It also performs MAC learning, priority assignment, and trunking functions.
2.7
* *
Other Internal Memory blocks
Several internal tables are required and are described as follows: Network Management (NM) Database - The NM database contains the information in the statistics counters and MIB. MAC address Control (MCLT) Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table.
2.8
Light Management and Configuration
One extra port is dedicated to the CPU via the CPU interface module. Two modes this port can operate: lightly managed or unmanaged mode. The different between these modes is tx/rx Ethernet frame and receiving interrupt due to the lack of constant attention or processing power from the CPU. The CPU interface supports a serial and an I2C interface, which provides an easy and lower cost way to configure the system for reduced management. Supported CPU interface modes are 1. Lightly Managed serial mode. Configuration registers access, Control frame and CPU transmit/receive packets are sent through a synchronous serial interface (SSI) bus. 2. Unmanaged mode. The ZL50404 can be configured by EEPROM using an IC interface at bootup, or via a synchronous serial interface (SSI) otherwise. All configuration registers and internal control blocks are accessible by the interface. However, the CPU cannot receive or transmit frames nor will it receive any interrupt information. The ZL50404 CPU interface provides for easy and effective management of the switching system. Figure 3 on page 18 provides an overview of the SSI interface.
17
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
Processor
Serial Out Serial In Strobe
ZL50404
Synchronous Serial Interface
3-bit Address Bus 16-bit Data Bus CS W R
Address
I/O Data MUX
Index Reg 1 (Addr = 1)
Index Reg 0 (Addr = 0)
Config Data Reg (Addr = 2)
CPU Frame Reg (Addr = 3)
Command/ Status Reg (Addr = 4)
Interrupt Reg (Addr = 5)
Control Command 1 Reg (Addr = 6)
Control Command 2 Reg (Addr = 7)
16-bit Address
8-bit Data Bus
8/16-bit Data Bus
8/16-bit Data Bus
Internal Registers Inderect Access
CPU frame Transmit CPU frame Receive FIFO FIFO
Control Control Command 1 Command 1Transmit Receive FIFO FIFO
Control Command 2 Transmit FIFO
Interrupt
Figure 3 - Overview of the ZL50404 SSI Interface
2.9 2.9.1
Register Configuration, Frame Transmission, and Frame Reception Register Configuration
The ZL50404 has many programmable parameters, covering such functions as QoS weights, VLAN control, and port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters are contained in 8-bit configuration registers. The ZL50404 allows indirect access to these registers, as follows: * In serial mode, address, command and data are shifted in serially. To access the configuration register, only one "index" registers (addresses 000b) needs to be written with the configuration register address. The desired data can be written into "configure data" register (address 010b). For example, if "XX" is required to be written to register "YY", a write of "YY" is required to write to address "000b" (Index register). Then, a write of "XX" is required to write to address "010b" (Conig Data Register). This completes the register write and register "YY" will contain the value of "XX". Similarly, to read the value in the register addressed by the index register, the "configure data" register can now simply be read.
*
18
Zarlink Semiconductor Inc.
ZL50404
*
Data Sheet
ZL50404 supports incremental read/write. If CPU requires to read or write to the configuration register incrementally, CPU only has to write to index register once with the MSB of configuration register address set and then CPU can continuously reading or writing to "configure data" register (010b). ZL50404 supports special register-write in serial mode. This allows CPU to write to two consecutive configuration registers in a single write operation. By writing to bit[14] of configuration register address, CPU can write 16-bit data to address 010b. Lower 8 bit of data is for the address specified in index register and upper 8 bit of data is for the address + 1.
15 INC R/W 14 SP W 13 12 11 12 Bit Register Address 0
*
Reserved
In summary, access to the many internal registers is carried out simply by directly accessing only two registers - one register to indicate the index of the desired parameter, and one register to read or write a value. Of course, because there is only one bus master, there can never be any conflict between reading and writing the configuration registers.
2.9.2
* *
Rx/Tx of Standard Ethernet Frames
To transmit a standard Ethernet frame from the CPU in lightly managed serial mode: The CPU writes a "data frame" register (address 011) with the data it wants to transmit (minimum 64 bytes). After writing all the data, it then writes the frame size, destination port number, and frame status. The ZL50404 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact that the frame originated from the CPU. The CPU receives an interrupt when an Ethernet frame is available to be received. Frame information arrives first in the data frame register. This includes source port number, frame size, and VLAN tag. The actual data follows the frame information. The CPU uses the frame size information to read the frame out.
To receive a frame into the CPU in lightly managed serial mode: * * *
Although there is the ability to Tx/Rx Ethernet Frames via the serial interface in lightly managed mode, the ZL50404 is not meant to be used in a fully managed system. The speed of the serial interface limits management capability. For example, if the system is trying to implement port security, it would require a faster interface between the CPU and the ZL50404, such as the 8/16-bit interface or the serial + MII interface found on the ZL50405.
2.9.3
Control Frames
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle special "Control frames," generated by the ZL50404 and sent to the CPU. These proprietary frames are related to such tasks as statistics collection, MAC address learning, and aging, etc... All Control frames are up to 40 bytes long. Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that the register accessed is the "Control frame data" register (address 111). Specifically, there are eight types of control frames generated by the CPU and sent to the ZL50404: Memory read request Memory write request Learn Unicast MAC address Delete Unicast MAC address Search Unicast MAC address Learn Multicast MAC address
19
Zarlink Semiconductor Inc.
ZL50404
Delete Multicast MAC address Search Multicast MAC address
Data Sheet
Note: Memory read and write requests by the CPU may include all internal memories which include statistic counters, Mac address control link table and the 2Mbit (256KB) memory block. In addition, there are seven types of Control frames generated by the ZL50404 and sent to the CPU: Interrupt CPU when statistics counter rolls over Response to memory read request from CPU Learn Unicast MAC address Delete Unicast MAC address Delete Multicast MAC address Response to search Unicast MAC address request from CPU Response to search Multicast Mac address request from CPU
The format of the Control Frame is described in the processor interface application note. Although there is the ability to Tx/Rx Control Frames via the serial interface in lightly managed mode, the ZL50404 is not meant to be used in a fully managed system. The speed of the serial interface limits management capability. For example, if the system is trying to manage the MAC learning/deletion, it would require a faster interface between the CPU and the ZL50404, such as the 8/16-bit interface found on the ZL50405.
2.10
I2C Interface
The IC interface serves the function of configuring the ZL50404 at boot time. The master is the ZL50404, and the slave is the EEPROM memory. The IC interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request / acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure 4 on page 20 depicts the data transfer format. The slave address is the memory address of the EEPROM. Refer to "ZL50404 Register Description" on page 44 for IC address for each register.
START SLAVE ADDRESS R/W ACK DATA 1 (8bits) ACK DATA 2 ACK DATA M ACK STOP
Figure 4 - Data Transfer Format for IC Interface
2.10.1
Start Condition
Generated by the master (in our case, the ZL50404). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the IC bus is free, both lines are High.
2.10.2
Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the EEPROM. The first seven bits of the first data byte make up the slave address.
2.10.3
Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master transmitter sets this bit to W; a master receiver sets this bit to R.
20
Zarlink Semiconductor Inc.
ZL50404
2.10.4 Acknowledgment
Data Sheet
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An acknowledgment pulse follows every byte transfer. If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the transfer. If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let the master generate the Stop condition.
2.10.5
Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an acknowledge bit. Data is transferred MSB first.
2.10.6
Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
2.11
Synchronous Serial Interface
The synchronous serial interface (SSI) serves the function of configuring the ZL50404 not at boot time but via a PC. The PC serves as master and the ZL50404 serves as slave. The protocol for the synchronous serial interface is nearly identical to the IC protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time. 3 ID bits are used to allow up to eight ZL50404 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. To reduce the number of signals required, the register address, command and data are shifted in serially through the DATAIN pin. STROBE- pin is used as the shift clock. DATAOUT pin is used as data return path. Each command consists of four parts. * * * * START pulse Register Address Read or Write command Data to be written or read back
Write operation can be aborted in the middle by sending an ABORT pulse to the ZL50404. Read operation can only be aborted before issuing the read command to the ZL50404. A START command is detected when DATAIN is sampled high when STROBE- rise and DATAIN is sampled low when STROBE- fall. An ABORT command is detected when DATAIN is sampled low when STROBE- rise and DATAIN is sampled high when STROBE- fall.
21
Zarlink Semiconductor Inc.
ZL50404
2.11.1 Write Command
Data Sheet
STROBE2 Extra clocks after last transfer
D0
ID0
ID1
ID2
A0
A1 ADDR
A2
W CMD
D0 D1 D2
D3
...
D12
D13
D14
D15
START
ID
DATA
Figure 5 - Serial Interface Write Command Functional Timing
2.11.2
Read Command
All registers in ZL50404 can be modified through this synchronous serial interface.
STROBE-
D0
ID0
ID1
ID2
A0 A1 A2 ADDR
R CMD DATA D0 D1 D2 ...
D12 D13 D14 D15
START AUTOFD-
ID
Figure 6 - Serial Interface Read Command Functional Timing
2.12
Timeout Reset Monitor
The ZL50404 supports a state machine monitoring block which can trigger a reset or interrupt if any state machine is determined to be stuck in a non-idle state for more than 5 seconds. This feature is enabled via a bootstrap pin (TSTOUT12). It also requires some register configuration via the CPU interface. See Programming Timeout Reset application note for more information.
2.13
JTAG
An IEEE1149.1 compliant test interface is provided for boundary scan.
3.0
3.1
ZL50404 Data Forwarding Protocol
Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. The memory (SRAM) interface is a 64-bit bus, connected to internal memory block. The Receive DMA (RxDMA) is responsible for multiplexing the data and the address. On a port's "turn," the RxDMA will move 8 bytes (or up to the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB). Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
22
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination MAC addresses of the frame. The search engine places a switch response in the switch response queue of the frame engine when done. Among other information, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward. But first, the TxQ manager has to decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct per-port-per-class TxQ. The switch response will come with 8 classified results. The TxQ manager will map this result into the per-port-per-class queue. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames' FCB's. There is one linked list for each transmission class for each port. There are 2 transmission classes for each of the 4 RMAC ports, and 4 classes for the MMAC port - a total of 16 unicast queues. The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release requests. The frame is transmitted from the TxFIFO to the line.
3.2
Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the multicast packet's destinations. If so, then the frame is dropped at some destinations but not others, and the FCB is not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames). There are 2 multicast queues for each of the 4 RMAC ports. There are 4 multicast queues for the MMAC port. The mapping from the classified result to the priority queue is the same as the unicast traffic. By default, for the RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the MMAC port, to map the 8 transmit priorities into 4 multicast queues, the LSB are discarded. The priority mapping can be modified through memory configuration command. The multicast queue that is in FIFO format shares the space in the 2M bits internal memory block. The size and starting address can also be programmed through memory configuration command. During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to which the frame is destined.
3.3
Frame Forwarding To and From CPU
Frame forwarding from the CPU port to a regular transmission port is nearly the same as forwarding between transmission ports. The only difference is that the physical destination port must be indicated in addition to the destination MAC address. Frame forwarding to the CPU port is nearly the same as forwarding to a regular transmission port. The only difference is in frame scheduling. Instead of using the patent-pending Zarlink Semiconductor scheduling algorithms, scheduling for the CPU port is simply based on strict priority. That is, a frame in a high priority queue will always be transmitted before a frame in a lower priority queue. There are four output queues to the CPU and one receive queue.
23
Zarlink Semiconductor Inc.
ZL50404
4.0
4.1
* * * * * * *
Data Sheet
Search Engine
Search Engine Overview
The ZL50404 search engine is optimized for high throughput searching, with enhanced features to support: Up to 4K of Unicast MAC addresses/Multicast MAC addresses 8 groups of port trunking Traffic classification into 2 (or 4 for MMAC) transmission priorities, and 2 drop precedence levels Packet filtering based on Mac address, Protocol or Logical Port number Security Individual Flooding, Broadcast, Multicast Storm Control MAC address learning and aging
4.2
Basic Flow
Shortly after a frame enters the ZL50404 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. Among the information extracted are the source and destination MAC addresses, and whether the frame is unicast or multicast or broadcast. Requests are sent to the SRAM to locate the associated entries in the MCT table. When all the information has been collected from the SRAM, the search engine has to compare the MAC address on the current entry with the MAC address for which it is searching. If it is not a match, the process is repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address unknown) or flooding (destination MAC address unknown). If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the source and destination MAC addresses. When all the information is compiled, the switch response is generated, as stated earlier. The search engine also interacts with the CPU with regard to learning and aging.
4.3 4.3.1
Search, Learning, and Aging MAC Search
The search block performs source MAC address and destination MAC address searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. In port based VLAN mode, a bitmap is used to determine whether the frame should be forwarded to the outgoing port. The main difference in this mode is that the bitmap is not dynamic. Ports cannot enter and exit groups because of real-time learning made by a CPU. The MAC search block is also responsible for updating the source MAC address timestamp used for aging.
24
Zarlink Semiconductor Inc.
ZL50404
4.3.2 Learning
Data Sheet
The learning module learns new MAC addresses and performs port change operations on the MCT database. The goal of learning is to update this database as the networking environment changes over time. When CPU reporting is enabled, learning and port change will be performed when the CPU request queue has room, and a "Learn MAC Address" message is sent to the CPU. When fast learning mode is enabled, learning and port change will be performed when and a latter "Learn MAC Address" message is sent to the CPU when CPU queue has room.
4.3.3
Aging
Aging time is controlled by register 400h and 401h. The aging module scans and ages MCT entries based on a programmable "age out" time interval. As we indicated earlier, the search module updates the source MAC address timestamps for each frame it processes. When an entry is ready to be aged, the entry is removed from the table, and a "Delete MAC Address" message is sent to inform the CPU. Supported MAC entry types are: dynamic, static, source filter, destination filter, source and destination filter, secure and multicast MAC address. Only dynamic entries can be aged; all others are static. The MAC entry type is stored in the "status" field of the MCT data structure.
4.4
MAC Address Filtering
The ZL50404's implementation of intelligent traffic switching provides filters for source and destination MAC addresses. This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and broadcast traffic. MAC address filtering allows the ZL50404 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem.
4.5
Protocol Filtering
Packet filtering can be performed based on protocol type field in the packets. Up to eight protocols can be programmed to filter or allow packet to pass through the switch.
4.6
Logical Port Filtering
Similar to protocol filtering, if the packet's logical ports match the programmable registers, the packet can be filtered or passed through the switch. Up to eight programmable ports and one ranges can be assigned.
4.7
Quality of Service
Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic), and improved loss characteristics. Traditional Ethernet networks have had no prioritization of traffic. Without a protocol to prioritize or differentiate traffic, a service level known as "best effort" attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. In a congested network or when a low-performance switch/router is overloaded, "best effort" becomes unsuitable for delay-sensitive traffic and mission-critical data transmission. The advent of QoS for packet-based systems accommodates the integration of delay-sensitive video and multimedia traffic onto any existing Ethernet network. It also alleviates the congestion issues that have previously
25
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
plagued such "best effort" networking systems. QoS provides Ethernet networks with the breakthrough technology to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth. Extensive core QoS mechanisms are built into the ZL50404 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port. In the ZL50404, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class. Frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. For example, the overall service given to frames and packets in the premium class will be better than that given to the standard class; the premium class is expected to experience lower loss rate or delay. The ZL50404 supports the following QoS techniques: * * * * In a port-based setup, any station connected to the same physical port of the switch will have the same transmit priority. In a tag-based setup, a 3-bit field in the VLAN tag provides the priority of the packet. This priority can be mapped to different queues in the switch to provide QoS. In a TOS/DS-based set up, TOS stands for "Type of Service" that may include "minimize delay," "maximize throughput," or "maximize reliability." Network nodes may select routing paths or forwarding behaviours that are suitably engineered to satisfy the service request. In a logical port-based set up, a logical port provides the application information of the packet. Certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications, such as VoIP.
4.8
Priority Classification Rule
Figure 7 shows the ZL50404 priority classification rule.
Fix Port Priority? No
Yes
Use Default port settings
TOS Precedence over VLAN? (QOSC Register bit 5) No Yes
Yes
Use VLAN priority
VLAN Tag? No Yes
No
IP Frame? Yes No Use TOS
IP Frame? No Use Default port settings
Use Logical Port? Yes Use logical port
Figure 7 - Priority Classification Rule
26
Zarlink Semiconductor Inc.
ZL50404
4.9 Port Based VLAN
The ZL50404 supports port based VLAN for simple VLAN setup.
Data Sheet
An administrator can use the PVMAP Registers to configure the ZL50404 for port-based VLAN (see "See "Register Definition" on page 44). The ZL50404 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50404 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded.
Destination Port Numbers Bit Map Port Registers Register for Port #0 PVMAP00_0[3:0] to PVMAP00_1[1:0] Register for Port #1 PVMAP01_0[3:0] to PVMAP01_1[1:0] Register for Port #2 PVMAP02_0[3:0] to PVMAP02_1[1:0] ... Register for Port #9 PVMAP09_0[3:0] to PVMAP09_1[1:0] 0 0 0 0 9 0 0 0 ... 2 1 1 0 1 1 0 0 0 0 1 0
Table 3 - Port-Based VLAN Mapping For example, in the above table a 1 denotes that an outgoing port is eligible to receive a packet from an incoming port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port. In this example: * * * Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2. Data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2. Data packets received at port #2 are NOT eligible to be sent to ports 0 and 1.
5.0
5.1
Frame Engine
Data Forwarding Summary
When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface. A switch request is sent to the Search Engine. The Search Engine processes the switch request. A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast, and its destination port or ports. On receiving the response, the Frame Engine will check all the QoS related information and decide if this frame can be forwarded. A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling Queue (TxSch Q) or Queues. There are 2 TxSch Q for each RMAC port (and 4 per MMAC port), one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service).
27
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
(The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The older HOL between the two queues goes first. The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port.
5.2
Frame Engine Details
This section briefly describes the functions of each of the modules of the ZL50404 frame engine.
5.2.1
FCB Manager
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. The FCB manager is also responsible for enforcing buffer reservations and limits that will be used for QoS control and source port flow control. The default values can be determined by referring to Chapter 7. The frame buffer is managed in a 128bytes block unit. During initialization, this block will link all the available blocks in a free buffer list. When each port is ready to receive, this module hands the buffer handle to each requesting port. The FCB manager will also link the released buffer back into the free buffer list.
5.2.2
Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch request.
5.2.3
RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made.
5.2.4
TxQ Manager
First, the TxQ manager checks the per-class queue status and global reserved resource situation, and using this information, makes the frame dropping decision after receiving a switch response. The dropping decision includes the head-of-link blocking avoidance if the source port is not flow control enabled. If the decision is not to drop, the TxQ manager links the unicast frame's FCB to the correct per-port-per-class TxQ and updates the FCB information. If multicast, the TxQ manager writes to the multicast queue for that port and class and also update the FCB information including the duplicate count for this multicast frame. The TxQ manager can also trigger source port flow control for the incoming frame's source if that port is flow control enabled. Second, the TxQ manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port control module. The detail of the QoS decision guideline is described in chapter 5.
5.2.5
Port Control
The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control module requests that the buffer be released.
5.2.6
TxDMA
The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules.
28
Zarlink Semiconductor Inc.
ZL50404
6.0
6.1
Data Sheet
Quality of Service and Flow Control
Model
Quality of service is an all-encompassing term for which different people have different interpretations. In general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. The manager can then subdivide the applications into classes and set up a service contract with each. The contract may consist of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to the switch. As an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide additional assurances about our switch's performance. Table 4 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. MMAC port actually has four total transmission priorities. TotalAssured Bandwidth (user defined)
50 Mbps
Goals
Low Drop Probability (low-drop)
Apps: phone emulation. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed. calls, circuit
High Drop Probability (high-drop) Apps: training video.
Latency: < 1 ms. Drop: No drop if P3 not oversubscribed; first P3 to drop otherwise.
Highest transmission priority, P3
Middle transmission priority, P2
37.5 Mbps
Apps: interactive apps, Web business.
Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed.
Apps: non-critical interactive apps.
Latency: < 4-5 ms. Drop: No drop if P2 not oversubscribed; firstP2 to drop otherwise.
Low transmission priority, P1
12.5 Mbps
Apps: emails, file backups.
Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed.
Apps: casual web browsing.
Latency: < 16 ms desired, but not critical. Drop: No drop if P1 not oversubscribed; first to drop otherwise.
Total
100 Mbps Table 4 - Two-dimensional World Traffic
A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. However, such leniency must not degrade the quality of service (QoS) received by well-behaved classes. As Table 4 illustrates, the six traffic types may each have their own distinct properties and applications. As shown, classes may receive bandwidth assurances or latency bounds. In the table, P3, the highest transmission class, requires that all frames be transmitted within 1 ms, and receives 50% of the 100 Mbps of bandwidth at that port.
29
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
Best-effort (P0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any traffic to offer. It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the ZL50404, each RMAC port will support two total classes, and the MMAC port will support four classes. We will discuss the various modes of scheduling these classes in the next section. In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should rarely lose packets. But poorly behaved users-users who send frames at too high a rate - will encounter frame loss, and the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped, and then all frames in the worst case. Table 4 shows that different types of applications may be placed in different boxes in the traffic table. For example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the category of low-loss, low-latency traffic.
6.2
Two QoS Configurations
There are two basic pieces to QoS scheduling in the MMAC port of ZL50404: strict priority (SP) or weighted fair queuing (WFQ). The only configuration for a RMAC port is strict priority between the two queues.
6.2.1
Strict Priority
When strict priority is part of the scheduling algorithm, if a queue has any frame to transmit, it goes first. For RMAC ports, this is an easy way to provide the different service. For all recognizable traffic, the bandwidth is guaranteed to 100% of the line rate. This scheme works as long as the overall high priority bandwidth is not over the line rate and the latency on all the low priority traffic is don't care. The strict priority queue in the MMAC port is similar to RMAC ports other than having 4 queues instead of 2 queues. The priority queue P0 can be scheduled only if the priority queue P1 is empty, so as to priority queues P2 and P3. The lowest priority queue is treated as best effort queue. Because we do not provide any assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the ZL50404, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. We only drop frames from best effort and strict priority queues when queue size is too long or global / class buffer resources become scarce.
6.2.2
Weighted Fair Queuing
In some environments - for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential, WFQ may be preferable to a strict assurance scheduling discipline. The ZL50404 provides this kind of scheduling algorithm on MMAC port only. The user sets four WFQ "weights" such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with granular within 2%. In WFQ mode, though we do not assure frame latency, the ZL50404 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control.
6.3
WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified parameters. The following table summarizes the behavior of the WRED logic. Px > WRED_L1 High Drop Low Drop X% Y% Px > WRED_L2 100% Z% BM Reject 100% 100%
Table 5 - WRED Logic Behaviour
30
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
Px is the total byte count, in the priority queue x, can be the strict priority queue of RMAC ports and higher 3 priority queues for MMAC port. The WRED logic has two drop levels, depending on the value of Px. Each drop level has defined high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. All packets will be dropped only if the system runs out of the specific buffer resource, per class buffer or per source port buffer. The WRED thresholds of each queue can be programmed by the QOS control registers (refer to the register group 8). See Programming QoS Registers application note for more information.
6.4
Shaper
Although traffic shaping is not a primary function of the ZL50404, the chip does implement a shaper for every queue in the MMAC port. Our goal in shaping is to control the average rate of traffic exiting the ZL50404. If shaper is enabled, strict priority will be applied to that queue. The priority between two shaped queue is the same as in strict priority scheduling. Traffic rate is set using a programmable whole number, no greater than 64. For example, if the setting is 32, then the traffic rate transmit out of the shaped queue is 32/64 * 100 Mbps = 50 Mbps. See Programming QoS Register application note for more information. Also, when shaping is enabled, it is possible for a queue to explode in length if fed by a greedy source. The reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line is idle. Though we do have global resource management, we do nothing other than per port WRED to prevent this situation locally. We assume the traffic is policed at a prior stage to the ZL50404 or WRED dropping is fine and shall restrain this situation.
6.5
Rate Control
The ZL50404 provides a rate control function on its RMAC ports. This rate control function applies to both the incoming and outgoing traffic aggregate on each RMAC port. It provides a way of reducing the average rate below full wire speed. Note that the rate control function does not shape or manipulate any particular traffic class. Furthermore, though the average rate of the port can be controlled with this function, the peak rate will still be full line rate. Two principal parameters are used to control the average rate for a RMAC port. A port's rate is controlled by allowing, on average, M bytes to be transmitted every N microseconds. Both of these values are programmable. The user can program the number of bytes in 8-byte increments, and the time may be set in units of 10us or 1ms. The value of M/N will, of course, equal the average data rate of the traffic aggregate on the given RMAC port. Although there are many (M,N) pairs that will provide the same average data rate performance, the smaller the time interval N, the "smoother" the output pattern will appear. In addition to controlling the average data rate on a RMAC port, the rate control function also manages the maximum burst size at wire speed. The maximum burst size can be considered the memory of the rate control mechanism; if the line has been idle for a long time, to what extent can the port "make up for lost time" by transmitting a large burst? This value is also programmable, measured in 8-byte increments. Example: Suppose that the user wants to restrict Fast Ethernet port P's average departure rate to 32 Mbps - 32% of line rate - when the average is taken over a period of 10 ms. In an interval of 10 ms, exactly 40000 bytes can be transmitted at an average rate of 32 Mbps. So how do we set the parameters? The rate control parameters are contained in an internal RAM block accessible through the CPU port (See Programming QoS Registers application note and Processor interface application note). The data format is shown below. 63:40 0 39:32 Time interval 31:16 Maximum burst size 15:0 Number of bytes
31
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
As we indicated earlier, the number of bytes is measured in 8-byte increments, so the 16-bit field "Number of bytes" should be set to 40000/8, or 5000. In addition, the time interval has to be set to 10 in units of 1 ms. Though we want the average data rate on port P to be 32 Mbps when measured over an interval of 10 ms, we can also adjust the maximum number of bytes that can be transmitted at full line rate in any single burst. Suppose we wish this limit to be 12 kilobytes. The number of bytes is measured in 8-byte increments, so the 16-bit field "Maximum burst size" is set to 12000/8, or 1500. The action on the incoming traffic and outgoing traffic when credit is not available are different. For the outgoing traffic, the queued frames will be held in the queue until the credit become available. The consequence of this holding is the exploding queue size that may cause dropping on the receiving side. The capability of ZL50404 on this perspective is quite limited due to the small frame buffer on chip. The actions on the incoming traffic depending on the flow control state of that port. If the ingress port flow control is turned on, the XOFF flow control will be triggered when the credit is running lower than half of the maximum burst size. The XON will be triggered when the available credit is increased to above the threshold. If the port flow control is disabled, the received traffic will subject to WRED depending on the credit availability. If the none of the credit is available, all received frame will be dropped. If only a quarter of maximum burst credits are available, the frame that been marked as high drop will be drop 100%, the low drop frame will be dropped at ra%, If half of the maximum burst credits are available, high drop frame will be dropped at rb%. The ra% and rb% can be programmed by RDRC2 register.
6.6
Buffer Management
Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the ZL50404. Our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in Figure 8 on page 33. As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first enters the ZL50404, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying. Six reserved sections, one for each of the first six priority classes, ensure a programmable number of FDB slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, a frame is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only four transmission scheduling queues for RMAC ports, but as far as buffer usage is concerned, there are still eight distinguishable classes. Another segment of the FDB reserves space for each of the 6 ports -- 5 ports for Ethernet and one CPU port (port number 8). Two parameters can be set, one for the source port reservation for RMAC ports and CPU port, and one for the source port reservation for the MMAC port. These 6 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in the six priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared pool. Once the shared pool is full the frames are allocated in the section reserved for the source port. The following registers define the size of each section of the Frame data Buffer: PR100- Port Reservation for RMAC Ports PRM- Port Reservation for MMAC Port SFCB- Share FCB Size C1RS- Class 1 Reserve Size C2RS- Class 2 Reserve Size C3RS- Class 3 Reserve Size
32
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
Temporary reservation Rpri1
Per Class Reservation
Rpri2
Rpri3
Shared Pool S
Per Source Port Reservation
Rp0
Rp1
Rp2
Rp3
Rp8
Rp9
Figure 8 - Buffer Partition Scheme Used to Implement Buffer Management in the ZL50404
6.6.1
Dropping When Buffers Are Scarce
As already discussed, the WRED mechanism may drop frames on output queue status. In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer management is to make sure that such dropping causes as little blocking as possible. If a received frame is dispatched to the best effort queue, the buffer management will check on the overall buffer situation plus the output queue status to decide the frame drop condition. If the source port has not enough buffer for it, the frame will be dropped. If the output queue reach the UCC (unicast congest control) and the shared buffer has run out, the frame will be dropped by b%. If the output queue reach the UCC and the source port reservation is lower than the buffer low threshold, the frame will be dropped. All the dropping functions are disabled if the source port is flow control capable.
6.7
ZL50404 Flow Control Basics
Because frame loss is unacceptable for some applications, the ZL50404 provides a flow control option. When flow control is enabled, scarcity of source port buffer space may trigger a flow control signal; this signal tells a source port sending a packet to this switch, to temporarily hold off. While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not, are halted. A single packet destined for a congested output can block other packets destined for un-congested outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. On the other hand, the ZL50404 will still prioritize the received frame disregarding the outgoing port flow control capability. If a frame is classified as high priority, it is still subjected to the WRED, which means the no-loss on the high priority queue is not guaranteed. To resolve this situation, the user may set the output port WRED threshold so high that may never be reached, or program the priority mapping table in the queue manager to map all the traffic to best effort queue on the flow control capable port. The first method has side impact on the global resource management since the port may hold too much per class resource that is scarce in the system. The second method, by nature, lost the benefit of prioritization.
6.7.1
Unicast Flow Control
For unicast frames, flow control is triggered by source port resource availability. Recall that the ZL50404's buffer management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a source port's reserved FDB slots have been used, then flow control Xoff is triggered. Xon is triggered when a port is currently being flow controlled, and all of that port's reserved FDB slots have been released.
33
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
Note that the ZL50404's per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled.
6.7.2
Multicast Flow Control
Flow control for multicast frames is triggered by a global buffer counter. When the system exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when the system returns below this threshold. Note: If per-port flow control is on, QoS performance will be affected.
6.8
Mapping to IETF Diffserv Classes
The mapping between priority classes discussed in this chapter and elsewhere is shown below. ZL50404 IETF P3 NM+EF P2 AF0 P1 AF1 P0 BE0
Table 6 - Mapping between ZL50404 and IETF Diffserv Classes for MMAC Port As the table illustrates, the classes of Table 6 are merged in pairs--one class corresponding to NM+EF, two AF classes, and a single BE class. For RMAC ports, the classes of Table 7 are merged in pairs--one class corresponding to NM+EF+AF1, AF0+ BE class. ZL50404 IETF P1 NM+EF P1 AF0 P0 AF1 P0 BE0
Table 7 - Mapping between ZL50404 and IETF Diffserv Classes for RMAC Ports Features of the ZL50404 that correspond to the requirements of their associated IETF classes are summarized in the table below. Network management (NM) and Expedited forwarding (EF) Assured forwarding (AF) Global buffer reservation for NM and EF Shaper for EF traffic on MMAC port Option of strict priority scheduling No dropping if admission controlled Four AF classes for MMAC port Programmable bandwidth partition, with option of WFQ service Option of delay-bounded service keeps delay under fixed levels even if not admission-controlled Random early discard, with programmable levels Global buffer reservation for each AF class Two BE classes for MMAC port Service only when other queues are idle means that QoS not adversely affected Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified as BE Table 8 - ZL50404 Features Enabling IETF Diffserv Standards
Best effort (BE)
34
Zarlink Semiconductor Inc.
ZL50404
6.9 Failover Backplane Feature
Data Sheet
The ZL50404 implements a hardware assisted link failure detection mechanism utilizing a Link Heart Beat (LHB) packet. The LHB packet format is defined as a 64-byte MAC control frame with a user defined opcode. The packet format is illustrated below: 01-80-c2-00-00-01 xx-xx-xx-xx-xx-xx 88-08 yy-yy 00-00-... CRC
Where "xx-xx-..." is the source port MAC address and "yy-yy" is the special opcode defined by register setup (LHBReg0,1). The opcode "00-01" is reserved for the flow control packet. The LHB is done between two compatible MACs providing this function. A timer parameter will be set for both the receiver and transmitter (LHBTimer). On the transmission side, the MAC will monitor the transmission activities. If there is no activity for more than the set period, a LHB packet will be sent to its link partner. Therefore, there should always be at least one packet transmitted from the MAC for every period specified. On the receiving side, the MAC will also monitor the activity. If there is no good packet received for more than 2X the set period, an alarm will be raised to the CPU. The LHB packet is only used by the ZL50404 to reset the timeout counter, it is ignored otherwise (i.e. not passed on within the system). See the Link Heart Beat Application Note for more information.
7.0
7.1
Port Trunking
Features and Restrictions
A port group (i.e. trunk) can include up to 4 physical ports. There are eight trunk groups total. Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address and destination MAC address. Three other options include source MAC address only, destination MAC address only, and source port (in bidirectional ring mode only). Load distribution for multicast is performed similarly. The ZL50404 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking group goes down, the ZL50404 can redistribute the traffic over to the remaining ports in the trunk with software assistance.
7.2
Unicast Packet Forwarding
The search engine finds the destination MCT entry, and if the status field says that the destination port found belongs to a trunk, then the trunk group number is retrieved. The source port of the packet is checked against the destination trunk group. If the source port belongs to the destination trunk group, the packet is discarded. A hash key, based on some combination of the source and destination MAC addresses for the current packet, selects the appropriate forwarding port, as specified in the Trunk_Hash registers. Each trunk has eight trunk_hash registers which selects one of the potential eight outgoing ports. The hash key provides a pseudo flow identifier which force the same flow to the same destination flow. As a result, the packet will always arrive in order.
7.3
Multicast Packet Forwarding
For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet based on the hash key.
35
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port trunking environment. * * The source port/group must be excluded from the forwarding. Select one port per trunk group to forward the packet to. This selection is based on hash key described in previous section.
8.0
8.1
Port Mirroring
Mirroring Features
Packets can be mirrored (duplicated) for network monitor purpose and/or network debug purpose. Three types of mirroring is available in ZL50404. 1. Source or Destination Mac address based 2. Flow based 3. Port based In source or destination mac address based mirroring, the "M" bit of the mirroring MAC address in the MCT is set. Also, the user need to specify the mirroring MAC address is source or destination of the packet. If source is selected, any packet received with the mirroring MAC address as source MAC address will be copied to the mirrored port. In the same way, if destination is selected, any packet received with mirroring MAC address as destination MAC address will be copied to the mirrored port. In flow based mirroring, a flow is established based on the source and destination mac address pair. When enabled, a packet with source and destination address match the pre-programmed source and destination mac address pair will be copied to the mirrored port. In reverse direction (source and destination match pre programmed destination and source), the flow can also be enabled and the frame will be copied to the mirrored port. In port based mirroring, traffic from any RMAC port can be mirrored to any RMAC port. The traffic from the source port can be either ingress or egress traffic. Up to two ports can be setup as mirrored ports. As a result, the traffic (both ingress and egress) of a specific port can be monitored by setting up both mirrored ports. Once a port is setup as mirrored port, it cannot be used for regular traffic. The mirrored port can be any port in the ZL50404.
8.2
Using port mirroring for loop back
To perform remote loop back test, port mirroring can be used to bounce back the packet to the source port to check the data path. The CPU needs to setup the remote device through the command channel to enable port mirroring in the remote device. A CPU packet is send to the port in test in Device A. The packet will be forwarded to the test port, external cable, the destination port in Device B, and loop back to itself, back to the cable and go back to Device A and the CPU. This way, the whole channel can be tested.
CPU
ZL50404 DEVICE A
ZL50404 DEVICE B
Figure 9 - Remote Loopback Test
36
Zarlink Semiconductor Inc.
ZL50404
9.0
9.1
Data Sheet
GPSI (7WS) Interface
GPSI connection
The RMAC ethernet port can function in GPSI (7WS) mode. In this mode, the TXD[0], RXD[0] serve as TX data, RX data and respectively. The link and duplex of the port can be controlled by programming the ECR register. Only port-based VLAN is supported with GPSI interface.
10.0
10.1
Clock Speed Requirements
System Clock (SCLK) speed requirement
SCLK is the primary clock for the ZL50404 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Configuration 5 port 10/100 Table 9 - SCLK Speed Requirements SCLK speed 25Mhz
10.2
RMAC Reference Clock (M_CLK) speed requirement
M_CLK is a 50MHz clock used for the RMAC ports (ports 0-3). If none of the RMAC ports are configured in RMII mode, a different clock frequency can be applied to M_CLK, as long as it's less than 50MHz. In this case, register USD must be set to provide an internal 1usec timing.
10.3
MMAC Reference Clock (REF_CLK) speed requirement
REF_CLK must be connected to SCLK for the MMAC port (port 9).
11.0
11.1
Hardware Statistics Counter
Hardware Statistics Counters List
ZL50404 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the delay exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager). The following is the wrapped signal sent to the CPU through the command block. 31 30 26 25 0
Status Wrapped Signal
Bytes Sent (D) Unicast Frame Sent Frame Send Fail Flow Control Frames Sent Non-Unicast Frames Sent
B[0] B[1] B[2] B[3] B[4]
0-d 1-L 1-U 2-I 2-u
37
Zarlink Semiconductor Inc.
ZL50404
B[5] B[6] B[7] B[8] B9] B[10] B[11] B[12] B[13] B[14] B[15] B[16] B[17] B[18] B[19] B[20] B[21] B[22] B[23] B[24] B[25] B[26] B[27] B[28] B[29] 3-d 4-d 5-d 6-L 6-U 7-l 7-u 8-L 8-U 9-L 9-U A-l A-u B-l B-u C-l C-U1 C-U D-l D-u E-l E-u F-l F-U1 F-U Bytes Received (Good and Bad) (D) Frames Received (Good and Bad) (D) Total Bytes Received (D) Total Frames Received Flow Control Frames Received Multicast Frames Received Broadcast Frames Received Frames with Length of 64 Bytes Jabber Frames Frames with Length Between 65-127 Bytes Oversize Frames Frames with Length Between 128-255 Bytes Frames with Length Between 256-511 Bytes Frames with Length Between 512-1023 Bytes Frames with Length Between 1024-1528 Bytes Fragments Alignment Error Undersize Frames CRC Short Event Collision Drop Filtering Counter Delay Exceed Discard Counter Late Collision
Data Sheet
Notation: X-Y X: Address in the contain memory
38
Zarlink Semiconductor Inc.
ZL50404
Y: d: L: U: U1: l: u: Size and bits for the counter D Word counter 24 bits counter bit[23:0] 8 bits counter bit[31:24] 8 bits counter bit[23:16] 16 bits counter bit[15:0] 16 bits counter bit[31:16]
Data Sheet
11.2 11.2.1
IEEE 802.3 HUB Management (RFC 1516) Event Counters READABLEOCTET
11.2.1.1
Counts number of bytes (i.e. octets) contained in good valid frames received. Frame size: > 64 bytes, < 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged No FCS (i.e. checksum) error No collisions
11.2.1.2
READABLEFRAME
Counts number of good valid frames received. Frame size: > 64 bytes, < 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged No FCS error No collisions
11.2.1.3
FCSERRORS
Counts number of valid frames received with bad FCS. Frame size: > 64 bytes, < 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged No framing error No collisions
39
Zarlink Semiconductor Inc.
ZL50404
11.2.1.4 ALIGNMENTERRORS
Counts number of valid frames received with bad alignment (not byte-aligned). Frame size: > 64 bytes, < 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged No framing error No collisions
Data Sheet
11.2.1.5
FrameTooLongs
Counts number of frames received with size exceeding the maximum allowable frame size. Frame size: > 64 bytes, > 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged FCS error: Framing error: No collisions don't care don't care
11.2.1.6
SHORTEVENTS
Counts number of frames received with size less than the length of a short event. Frame size: FCS error: Framing error: No collisions > 64 bytes, don't care don't care < 10 bytes
11.2.1.7
Runts
Counts number of frames received with size under 64 bytes, but greater than the length of a short event. Frame size: FCS error: Framing error: No collisions > 10 bytes, don't care don't care < 64 bytes
11.2.1.8
COLLISIONS
Counts number of collision events. Frame size: any size
40
Zarlink Semiconductor Inc.
ZL50404
11.2.1.9 LATEEVENTS
Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes). Frame size: any size
Data Sheet
Events are also counted by collision counter
11.2.1.10
VeryLongEvents
Counts number of frames received with size larger than Jabber Lockup Protection Timer (TW3). Frame size: > Jabber
11.2.1.11
DATARATEMISATCHES
For repeaters or HUB application only.
11.2.1.12
AUTOPARTITIONS
For repeaters or HUB application only.
11.2.1.13
FCS errors
TOTALERRORS
Sum of the following errors:
Alignment errors Frame too long Short events Late events Very long events
11.3 11.3.1
IEEE - 802.1 Bridge Management (RFC 1286) Event Counters INFRAMES
11.3.1.1
Counts number of frames received by this port or segment. Note: A frame received by this port is only counted by this counter if and only if it is for a protocol being processed by the local bridge function.
11.3.1.2
OUTFRAMES
Counts number of frames transmitted by this port. Note: A frame transmitted by this port is only counted by this counter if and only if it is for a protocol being processed by the local bridge function.
41
Zarlink Semiconductor Inc.
ZL50404
11.3.1.3 INDISCARDS
Data Sheet
Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process.
11.3.1.4
DELAYEXCEEDEDDISCARDS
Counts number of frames discarded due to excessive transmit delay through the bridge.
11.3.1.5
MTUEXCEEDEDDISCARDS
Counts number of frames discarded due to excessive size.
11.4 11.4.1
RMON - Ethernet Statistic Group (RFC 1757) Event Counters DROP EVENTS
11.4.1.1
Counts number of times a packet is dropped, because of lack of available resources. DOES NOT include all packet dropping -- for example, random early drop for quality of service support.
11.4.1.2
OCTETS
Counts the total number of octets (i.e. bytes) in any frames received.
11.4.1.3
BROADCASTPKTS
Counts the number of good frames received and forwarded with broadcast address. Does not include non-broadcast multicast frames.
11.4.1.4
MULTICASTPKTS
Counts the number of good frames received and forwarded with multicast address. Does not include broadcast frames.
11.4.1.5
CRCAlignErrors
> 64 bytes, < 1522 bytes if VLAN tag (1518 if no VLAN)
Frame size: No collisions:
Counts number of frames received with FCS or alignment errors
11.4.1.6
UNDERSIZEPKTS
Counts number of frames received with size less than 64 bytes. Frame size: No FCS error No framing error No collisions < 64 bytes,
42
Zarlink Semiconductor Inc.
ZL50404
11.4.1.7 OVERSIZEPKTS
Counts number of frames received with size exceeding the maximum allowable frame size. Frame size: FCS error Framing error No collisions 1522 bytes if VLAN tag (1518 bytes if no VLAN) don't care don't care
Data Sheet
11.4.1.8
FRAGMENTS
Counts number of frames received with size less than 64 bytes and with bad FCS. Frame size: Framing error No collisions < 64 bytes don't care
11.4.1.9
JABBERS
Counts number of frames received with size exceeding maximum frame size and with bad FCS. Frame size: Framing error No collisions > 1522 bytes if VLAN tag (1518 bytes if no VLAN) don't care
11.4.1.10
Collisions
Counts number of collision events detected. Only a best estimate since collisions can only be detected while in transmit mode, but not while in receive mode. Frame size: any size
11.4.1.11
Packet Count for Different Size Groups
for any packet with size = 64 bytes for any packet with size from 65 bytes to 127 bytes or any packet with size from 128 bytes to 255 bytes for any packet with size from 256 bytes to 511 bytes for any packet with size from 512 bytes to 1023 bytes for any packet with size from 1024 bytes to 1518 bytes
Six different size groups - one counter for each: Pkts64Octets Pkts65to127Octets Pkts128to255Octets Pkts256to511Octets Pkts512to1023Octets Pkts1024to1518Octets
Counts both good and bad packets.
43
Zarlink Semiconductor Inc.
ZL50404
11.5 Miscellaneous Counters
Data Sheet
In addition to the statistics groups defined in previous sections, the ZL50404 has other statistics counters for its own purposes. We have two counters for flow control - one counting the number of flow control frames received, and another counting the number of flow control frames sent. We also have two counters, one for unicast frames sent, and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called "frame send fail." This keeps track of FIFO under-runs, late collisions, and collisions that have occurred 16 times.
12.0
12.1
Register Definition
ZL50404 Register Description
IC Addr (Hex)
Register
Description
CPU Addr (Hex)
R/W
Default
Notes
0. ETHERNET Port Control Registers Substitute [N] with Port number (0..3,8,9) ECR1P"N" ECR2P"N" ECR3P"N" ECR4P"N" BUF_LIMIT FCC AVTCL AVTCH PVMAP"N"_0 PVMAP"N"_1 PVMAP"N"_3 PVMODE TRUNK"N" TRUNK"N"_ HASH10 TRUNK"N"_ HASH32 Port Control Register 1 for Port N Port Control Register 2 for Port N Port Control Register 3 for Port N Port Control Register 4 for Port N Frame Buffer Limit Flow Control Grant Period VLAN Type Code Register Low VLAN Type Code Register High Port "N" Configuration Register 0 Port "N" Configuration Register 1 Port "N" Configuration Register 3 VLAN Operating Mode Trunk Group N (0..7) Trunk Group N (0..7) Hash 10 Destination Port Trunk Group N (0..7) Hash 32 Destination Port 000 + 2N 001 + 2N 080 + 2N 081 + 2N 036 037 100 101 102 + 4N 103 + 4N 105 + 4N 170 200 + N 208 + 4N 209 + 4N R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 000-0 09 00A-0 13 014-0 1D 01E-0 27 NA NA 028 029 02A-0 33 034-0 3D 03E-0 47 048 NA NA NA 0C0 000 000 018 040 003 000 081 0FF 0FF 000 000 000 000 000
1. VLAN Control Registers Substitute [N] with Port number (0..3,8,9)
2. TRUNK Control Registers
Table 10 - Register Description
44
Zarlink Semiconductor Inc.
ZL50404
CPU Addr (Hex) 20A + 4N 20B + 4N 228 + 2N 229 + 2N IC Addr (Hex) NA NA NA NA
Data Sheet
Register TRUNK"N"_ HASH54 TRUNK"N"_ HASH76 MULTICAST_ HASH"N"-0 MULTICAST_ HASH"N"-1 MAC0 MAC1 MAC2 MAC3 MAC4 MAC5 INT_MASK INTP_MASK"N" RQS RQSS MAC01 MAC23 MAC9 AGETIME_LOW AGETIME_ HIGH SE_OPMODE 5. Global QOS Control QOSC UCC MCC MCCTH RDRC0
Description Trunk Group N (0..7) Hash 54 Destination Port Trunk Group N (0..7) Hash 76 Destination Port Multicast hash result N (0..7) mask byte 0 Multicast hash result N (0..7) mask byte 1 CPU MAC Address byte 0 CPU MAC Address byte 1 CPU MAC Address byte 2 CPU MAC Address byte 3 CPU MAC Address byte 4 CPU MAC Address byte 5 Interrupt Mask 0 Interrupt Mask for MAC Port 2N, 2N+1 Receive Queue Select Receive Queue Status Increment MAC port 0,1 address Increment MAC port 2,3 address Port 9 MAC address byte 5 MAC Address Aging Time Low MAC Address Aging Time High Search Engine Operating Mode QOS Control Unicast Congestion Control Multicast Congestion Control Multicast Congestion Threshold WRED Drop Rate Control 0
R/W R/W R/W R/W R/W
Default 000 000 0FF 0FF
Notes
3. CPU Port Configuration 300 301 302 303 304 305 306 310+N (310 -311) 323 324 325 326 329 400 401 403 500 510 511 512 513 R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W NA NA NA NA NA NA NA NA NA NA NA NA NA 049 04A NA 04B 068 069 NA 090 000 000 000 000 000 000 000 000 000 NA 000 000 000 05C 000 000 000 006 006 003 000
4. Search Engine Configurations
Table 10 - Register Description (continued)
45
Zarlink Semiconductor Inc.
ZL50404
CPU Addr (Hex) 514 515 518 519 51A 51B 530 531 532 533 540 541 542 543 550 - 557 558 IC Addr (Hex) 091 NA 074 075 076 077 056 057 058 05C 059 05A 05B 05D 0B3 0BA 0BB
Data Sheet
Register RDRC1 RDRC2 SFCB C1RS C2RS C3RS AVPML AVPMM AVPMH AVDM TOSPML TOSPMM TOSPMH TOSDML USER_PROTOCOL_[7 :0] USER_PROTOCOL_F ORCE _DISCARD[7:0] WLPP10 WLPP32 WLPP54 WLPP76 WLPE[7:0] WLPFD[7:0] USER_ PORT"N"_LOW USER_ PORT"N"_HIGH
Description WRED Drop Rate Control 1 WRED Drop Rate Control 2 Share FCB Size Class 1 Reserve Size Class 2 Reserve Size Class 3 Reserve Size VLAN Priority Map Low VLAN Priority Map Middle VLAN Priority Map High VLAN Discard Map TOS Priority Map Low TOS Priority Map Middle TOS Priority Map High TOS Discard Map User Define Protocol 0~7 User Define Protocol 7 To 0 Force Discard Enable Well known Logic Port Priority for 1 and 0 Well known Logic Port Priority for 3 and 2 Well known Logic Port Priority for 5 and 4 Well-known Logic Port Priority for 7 & 6 Well known Logic 7 To 0 Port Enable Well Known Logic 7 To 0 Port Force Discard Enable User Define Logical Port "N" Low (N=0-7) User Define Logical Port "N" High
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
Notes
560 561 562 563 564 565 570 + 2N 571 + 2N
R/W R/W R/W R/W R/W R/W R/W R/W
0A8 0A9 0AA 0AB 0AC 0AD 092-0 99 09A-0 A1
000 000 000 000 000 000 000 000
Table 10 - Register Description (continued)
46
Zarlink Semiconductor Inc.
ZL50404
CPU Addr (Hex) 590 591 592 593 594 595 5A0 5A1 5A2 5A3 5A4 600 601 602 603 604 605 606 607 608 609 60A 60B 610 611 612 IC Addr (Hex) 0A2 0A3 0A4 0A5 0A6 0A7 0AE 0AF 0B0 0B1 0B2 0BC 0BD 0BE N/A N/A N/A N/A N/A N/A N/A N/A 0FF N/A N/A N/A
Data Sheet
Register USER_ PORT1:0_ PRIORITY USER_ PORT3:2_ PRIORITY USER_ PORT5:4_ PRIORITY USER_ PORT7:6_PRI ORITY USER_PORT_ENABL E[7:0] USER_PORT_FORCE _DISCARD[7:0] RLOWL RLOWH RHIGHL RHIGHH RPRIORITY MII_OP0 MII_OP1 FEN MIIC0 MIIC1 MIIC2 MIIC3 MIID0 MIID1 USD DEVICE SUM LHBTimer LHBReg0 LHBReg1
Description User Define Logic Port 1 and 0 Priority User Define Logic Port 3 and 2 Priority User Define Logic Port 5 and 4 Priority User Define Logic Port 7 and 6 Priority User Define Logic 7 To 0 Port Enable User Define Logic 7 To 0 Port Force Discard Enable User Define Range Low Bit7:0 User Define Range Low Bit 15:8 User Define Range High Bit 7:0 User Define Range High Bit 15:8 User Define Range Priority MII Register Option 0 MII Register Option 1 Feature Registers MII Command Register 0 MII Command Register 1 MII Command Register 2 MII Command Register 3 MII Data Register 0 MII Data Register 1 One micro second divider Device id and test EEPROM Checksum Register Link heart beat time out timer LHB control filed value[7:0] LHB control filed value[15:8]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
Default 000 000 000 000 000 000 000 000 000 000 000 000 000 010 000 000 000 000 NA NA 000 002 000 000 000 000
Notes
6. MISC Configuration Register
Table 10 - Register Description (continued)
47
Zarlink Semiconductor Inc.
ZL50404
CPU Addr (Hex) 613 614 620 621 622 700 701 702 703 704 705 706 707 708 709 70A 70B 70C 710 711 800-809 820-829 IC Addr (Hex) N/A N/A 0BF 0C0 0C1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 04C-0 55 05E-0 67
Data Sheet
Register fMACCReg0 fMACCReg1 FCB_BASE_ADDR0 FCB_BASE_ADDR1 FCB_BASE_ADDR2 MIRROR_DEST_MAC 0 MIRROR_DEST_MAC 1 MIRROR_DEST_MAC 2 MIRROR_DEST_MAC 3 MIRROR_DEST_MAC 4 MIRROR_DEST_MAC 5 MIRROR_SRC_MAC0 MIRROR_SRC_MAC1 MIRROR_SRC_MAC2 MIRROR_SRC_MAC3 MIRROR_SRC_MAC4 MIRROR_SRC_MAC5 MIRROR_CONTROL RMAC_MIRROR0 RMAC_MIRROR1 8. Per Port QOS Control FCR"N" BMRC"N"
Description Forced MAC control filed value[7:0] Forced MAC control filed value[15:8] FCB Base Address Register 0 FCB Base Address Register 1 FCB Base Address Register 2 Mirror Destination Mac Address 0 Mirror Destination Mac Address 1 Mirror Destination Mac Address 2 Mirror Destination Mac Address 3 Mirror Destination Mac Address 4 Mirror Destination Mac Address 5 Mirror Source Mac Address 0 Mirror Source Mac Address 1 Mirror Source Mac Address 2 Mirror Source Mac Address 3 Mirror Source Mac Address 4 Mirror Source Mac Address 5 Port Mirror Control Register RMAC Mirror 0 RMAC Mirror 1 Flooding Control Register N (0..3,8,9) Broadcast/Multicast Rate Control N (0..3,8,9)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 000 000 000 060 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
Notes
7. Port Mirroring Controls
Table 10 - Register Description (continued)
48
Zarlink Semiconductor Inc.
ZL50404
CPU Addr (Hex) 840-843 IC Addr (Hex) 06A-0 71
Data Sheet
Register PR100_N
Description Port Reservation for RMAC Ports (Port 0..3)
R/W R/W
Default 006
Notes `d1536 /16=`d 96, `d96>> 4='h6 `d96 `d96x6 =`d576 , `d576> >4='h2 4 1/2 1/2 1/2
PR100_CPU PRM
Port Reservation for CPU Ports Port Reservation for MMAC Port
848 849
R/W R/W
073 072
006 024
PTH100_N PTH100_CPU PTHM QOSC"N"
Port Threshold for RMAC Ports (Port 0..3) Port Threshold for CPU Port Port Threshold for MMAC Port QOS Control (N=0 - 15) QOS Control (N=16 - 21) QOS Control (N=22 - 27) QOS Control (N=28 - 39)
860-863 868 869 880-88F 890-895 896-89B 89C-8A7 E00 E01 E02 E03 E10 E11 E12 E13 E14 E80 - E82 E90-E99 EA0-EA3
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/O R/O R/W R/W R/W R/W R/W RO RO RO
0C2-0 C9 0CB 0CA 078-0 87 NA 088-0 8D NA NA NA NA NA 0F6 0F7 0F8 0F9 0FA NA NA NA
003 003 012 000 000 000 000 000 001 NA NA 000 000 000 000 000 NA NA NA
E. SYSTEM DIAGNOSTIC DTSRL DTSRM TESTOUT0 TESTOUT1 MASK0 MASK1 MASK2 MASK3 MASK4 BOOTSTRAP[2:0] PRTFSMST-N (0-3,8,9) PRTQOSST"N" (0-3) Test Register Low Test Register Medium Testmux Output [7:0] Testmux Output [15:8] MASK Timeout 0 MASK Timeout 1 MASK Timeout 2 MASK Timeout 3 MASK Timeout 4 BOOTSTRAP Read Back Ethernet Ports Status Read Back RMAC Port [3:0] QOS and Queue Status
Table 10 - Register Description (continued)
49
Zarlink Semiconductor Inc.
ZL50404
CPU Addr (Hex) EA8 EA9 EAA EAB EAC EAD EB0-EB9 EBA EBB EBC EBD EC0 EC1 EC2 EC3 EC4 EC5 EC6 EC7 EC8 EC9 ECA ECB ECC ECD IC Addr (Hex) NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Data Sheet
Register PRTQOSST8A PRTQOSST8B PRTQOSST9A PRTQUSST9B CLASSQOSST PRTINTCTR QMCTRL"N" (0-3,8,9) QCTRL BMBISTR0 BMBISTR1 BMControl BUFF_RST FCB_HEAD_PTR0 FCB_HEAD_PTR1 FCB_TAIL_PTR0 FCB_TAIL_PTR1 FCB_NUM0 FCB_NUM1 BM_RLSFF_CTRL BM_RLSFF_INFO0 BM_RLSFF_INFO1 BM_RLSFF_INFO2 BM_RLSFF_INFO3 BM_RLSFF_INFO4 BM_RLSFF_INFO5 F. SYSTEM CONTROL GCR DCR
Description CPU Port QOS and Queue Status CPU Port QOS and Queue Status MMAC Port QOS and Queue Status MMAC Port QOS and Queue Status Class Buffer Status Buffer Interrupt Status Ports Queue Control Status Ports Queue Control Memory bist result Memory bist result Memory control Buffer Reset Pool FCB Head Pointer [7:0] FCB Head Pointer [15:8] FCB Tail Pointer [7:0] FCB Tail Pointer [15:8] FCB Number [7:0] FCB Init Start and FCB Number [14:8] Read control register Bm_rlsfifo_info[7:0] Bm_rlsfifo_info[15:8] Bm_rlsfifo_info[23:16] Bm_rlsfifo_info[31:24] Bm_rlsfifo_info[39:32] Fifo_cnt[2:0],Bm_rlsfifo_info[44: 40] Global Control Register Device Control Register
R/W RO RO RO RO RO R/W R/W R/W R/O R/O R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO
Default NA NA NA NA NA 000 000 000 NA NA 00F 000 000 000 000 000 000 006 000 NA NA NA NA NA NA
Notes
F00 F01
R/W RO
NA NA
000 NA
Table 10 - Register Description (continued)
50
Zarlink Semiconductor Inc.
ZL50404
CPU Addr (Hex) F02 F03 F04 FFF IC Addr (Hex) NA NA NA NA
Data Sheet
Register DCR1 DPST DTST DA
Description Device Control Register 1 Device Port Status Register Data read back register DA Register
R/W RO R/W RO RO
Default NA 000 NA 0DA
Notes
Table 10 - Register Description (continued)
12.2 12.2.1
* *
Directly Accessed Registers INDEX_REG0
Address bits [7:0] for indirectly accessed register addresses Address = 0 (write only)
12.2.2
* *
INDEX_REG1 (only needed for 8-bit mode)
Address bits [15:8] for indirectly accessed register addresses Address = 1 (write only)
12.2.3
* *
DATA_FRAME_REG
Data of indirectly accessed registers. (8 bits) Address = 2 (read/write)
12.2.4
* * *
CONTROL_FRAME_REG
CPU transmit/receive switch frames. (8/16 bits) Address = 3 (read/write) Format: - Send frame from CPU: In sequence) - Frame Data (size should be in multiple of 8-byte) - 8-byte of Frame status (Frame size, Destination port #, Frame O.K. status) - CPU Received frame: In sequence) - 8-byte of Frame status (Frame size, Source port #, VLAN tag) - Frame Data
12.2.5
* * *
COMMAND&STATUS Register
CPU interface commands (write) and status Address = 4 (read/write) When the CPU writes to this register Bit [0]: Bit [1]: Set Control Frame Receive buffer ready, after CPU writes a complete frame into the buffer. This bit is self-cleared. Set Control Frame Transmit buffer1 ready, after CPU reads out a complete frame from the buffer. This bit is self-cleared.
51
Zarlink Semiconductor Inc.
ZL50404
Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [7:6]:
Data Sheet
Set Control Frame Transmit buffer2 ready, after CPU reads out a complete frame from the buffer. This bit is self-cleared. Set this bit to indicate CPU received a whole frame (transmit FIFO frame receive done), and flushed the rest of frame fragment, If occurs. This bit will be self-cleared. Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit will be self-cleared. Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature can be used for software debug. For normal operation must be '0'. Reserved. Must be '0'
When the CPU reads this register: Bit [0]: Control Frame receive buffer ready, CPU can write a new frame 1 - CPU can write a new control command 1 0 - CPU has to wait until this bit is 1 to write a new control command 1 Control Frame transmit buffer1 ready for CPU to read 1 - CPU can read a new control command 1 0 - CPU has to wait until this bit is 1 to read a new control command Control Frame transmit buffer2 ready for CPU to read 1 - CPU can read a new control command 1 0 - CPU has to wait until this bit is 1 to read a new control command Transmit FIFO has data for CPU to read (TXFIFO_RDY) Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK) Transmit FIFO End Of Frame (TXFIFO_EOF) Reserved
Bit [1]:
Bit [2]:
Bit [3]: Bit [4]: Bit [5]: Bit [7:6]:
12.2.6
* * *
Interrupt Register
Interrupt sources (8 bits) Address = 5 (read only) When CPU reads this register Bit [0]: Bit [1]: Bit [2]: Bit [6:3]: Bit [7]: CPU frame interrupt Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU to read Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read Reserved Device Timeout Detected interrupt
Note: This register is not self-cleared. After reading CPU has to clear the bit writing 0 to it.
12.2.7
* * *
Control Command Frame Buffer1 Access Register
Address = 6 (read/write) When CPU writes to this register, data is written to the Control Command Frame Receive Buffer When CPU reads this register, data is read from the Control Command Frame Transmit Buffer1
52
Zarlink Semiconductor Inc.
ZL50404
12.2.8
* *
Data Sheet
Control Command Frame Buffer2 Access Register
Address = 7 (read only) When CPU reads this register, data is read from the Control Command Frame Transmit Buffer1
12.3 12.3.1
Indirectly Accessed Registers (Group 0 Address) MAC Ports Group ECR1Pn: Port N Control Register
12.3.1.1
IC Address 000 - 009; CPU Address:0000+2xN (N = port number) Accessed by CPU and IC (R/W) Bit [0] 1 - Flow Control Off 0 - Flow Control On (Default) When Flow Control On: * In half duplex mode, the MAC transmitter applies back pressure for flow control. * In full duplex mode, the MAC transmitter sends Flow Control frames when necessary. The MAC receiver interprets and processes incoming flow control frames. The Flow Control Frame Received counter is incremented whenever a flow control is received. When Flow Control Off: * In half duplex mode, the MAC transmitter does not assert flow control by sending flow control frame or jamming collision. * In full duplex mode, the Mac transmitter does not send flow control frames. The MAC receiver does not interpret or process the flow control frames. The Flow Control Frame Received counter is not incremented. Bit [1] Bit [2] Bit [4:3] 1 - Half Duplex - Only in 10/100 mode 0 - Full Duplex (Default) 1 - 10Mbps 0 - 100Mbps (Default) 00 - Enable Auto-Negotiation This enables hardware state machine for auto-negotiation. (Default) 01 - Limited Disable Auto-Negotiation This disables hardware state machine for speed auto-negotiation (use ECR1Pn[2:0] for configuration). Hardware will still poll PHY for link status. 10 - Force Link Down Disable the port. Hardware does not talk to PHY. 11 - Force Link Up The configuration in ECR1Pn[2:0] is used for (speed/duplex/flow control) setup. Hardware does not talk to PHY. Asymmetric Flow Control Enable. 0 - Disable asymmetric flow control (Default) 1 - Enable Asymmetric flow control When this bit is set and flow control is on (bit[0] = 0), the device does not send out flow control frames, but it's receiver interprets and processes flow control frames. Bit [7:6] SS - Spanning tree state (802.1D spanning tree protocol) 00 - Blocking: Frame is dropped 01 - Listening: Frame is dropped 10 - Learning: Frame is dropped. Source MAC address is learned. 11 - Forwarding: Frame is forwarded. Source MAC address is learned. (Default)
Bit [5]
53
Zarlink Semiconductor Inc.
ZL50404
12.3.1.2 ECR2Pn: Port N Control Register
IC Address: 00A-013; CPU Address:0001+2xN (N = port number) Accessed by CPU and IC (R/W) Bit[0]:
Data Sheet
Filter untagged frame 0: Disable (Default) 1: All untagged frames from this port are discarded or follow security option when security is enable Filter Tag frame 0: Disable (Default) 1: All tagged frames from this port are discarded or follow security option when security is enable Learning Disable 0: Learning is enabled on this port (Default) 1: Learning is disabled on this port Rate control timer select 0: 10 microsecond refreshing time (Default) 1: 1 millisecond refreshing time Reserved Security Enable. The ZL50404 checks the incoming data for one of the following conditions: * If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. * A MAC address is defined as secure when its entry at MAC table has static status and bit 0 is set to 1. MAC address bit 0 (the first bit transmitted) indicates whether the address is unicast or multicast. As source addresses are always unicast bit 0 is not used (always 0). ZL50404 uses this bit to define secure MAC addresses. * If the port is set as learning disable and the source MAC address of the incoming packet is not defined in the MAC address table or the MAC address is not associated to the ingress port. If any one of the conditions is met, the packet is forwarded based on these setting. 00 - Disable port security, forward packets as usual. (Default) 01 - Discard violating packets 1X - Reserved As well, if: * the port is configured to filter untagged frames and an untagged frame arrives, or * the port is configured to filter tagged frames and a tagged frame arrives, or * the packet has the source mac address on the source mac address filter list, or * the packet has the destination mac address on the destination mac address filter list, the packet will be handled according to: 0X - Discard violating packets 1X - Reserved
Bit[1]:
Bit[2]:
Bit[3]:
Bit[5:4] Bit[7:6]
54
Zarlink Semiconductor Inc.
ZL50404
12.3.1.3 ECR3Pn: Port N Control Register
IC Address: 014-01D; CPU Address:0080+2xN (N = port number) Accessed by CPU and IC (R/W) Bit[0]: Enable receiving short frame < 64B 0: Disable (Default) 1: Allow receiving short frame with correct CRC. Enable receiving long frame > 1522 0: Disable (Default) 1: Allow receiving long frame that smaller than "BUF_LIMIT" value Enable pad frame to 64B when transmitted 1: Disable (Default) 0: Allow padding to 64B Enable compress preamble 1: Only one byte preamble+SFD 0: Send standard preamble (Default) Number of bytes removed from the IFG. (Default 0) Link Heart Beat Transmit (RMAC ports only) 0: Disable (Default) 1: Enable
Data Sheet
Bit[1]:
Bit[2]:
Bit[3]:
Bit[6:4] Bit[7]
12.3.1.4
ECR4Pn: Port N Control Register
IC Address: 01E-027; CPU Address:0081+2xN (N = port number) Accessed by CPU and IC (R/W) Port 0 - 3 and Port 9: (RMAC Port & MMAC Port) Bit[0]: Enable TXCLK output. Active high 0: Disable (Default) 1: Txclk pin becomes output in GPSI or MII mode Enable RXCLK output. Active high 0: Disable (Default) 1: Rxclk pin becomes output in GPSI or MII mode Internal loopback. 0: Disable (Default) 1: Enable In this mode, the packet is looped back in the MAC layer before going out of the chip. You must force linkup at full duplex as well. External loopback is another level of system diagnostic which involves the PHY device to loopback the packet.
Bit[1]:
Bit[2]:
55
Zarlink Semiconductor Inc.
ZL50404
Bit[4:3]: RMAC interface mode: 00 - GPSI mode 01 - MII mode 10 - Reserved 11 - RMII mode (Default) MMAC interface mode (Port 9): 11 - MII mode (Default) Bit[5]: Frame loopback. 0: Disable frame from sending back to its source port. (Default) 1: Allow frame to send back to its source port
Data Sheet
In a regular ethernet switch, a packet should never be receive and forwarded to the same port. Setting the bit allows it to happen. This is not the same as an ingress MAC loopback. The destiniation MAC address has to be stored (learned) in the MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit[6]: Link Heart Beat Receive (RMAC ports only) 0: Disable (Default). Also clears all MAC LHB status. 1: Enable Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing.
Bit[7]:
Port 8: (CPU port) Bit[1:0]: Bit[2]: Reserved Enable special write to 2 registers in a single write operation. 0: Disable (Default) 1: Enable Reserved. Must be 00. Enable frame loop back. In a regular ethernet switch, a packet should never receive and forwarded to the same port. Setting the bit allows it to happen. 0: Disable frame from send back to its source port. (Default) 1: Allow frame to send back to its source port Reserved Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing.
Bit[4:3]: Bit[5]:
Bit[6]: Bit[7]:
56
Zarlink Semiconductor Inc.
ZL50404
12.3.1.5 BUF_LIMIT - Frame Buffer Limit
CPU Address:h036 Accessed by CPU (R/W) Bit[6:0]: Bit[7]: Frame Buffer Limit (max 4KB). Multiple of 64 bytes (Default 0x40) Reserved
Data Sheet
12.3.1.6
FCC - Flow Control Grant Period
CPU Address:h037 Accessed by CPU (R/W) Bit[2:0]: Bit[7:3]: Flow Control Grant Period (Default 0x3) Reserved
12.3.2 12.3.2.1
(Group 1 Address) VLAN Group AVTCL - VLAN Type Code Register Low
IC Address 028; CPU Address:h100 Accessed by CPU and IC (R/W) Bit[7:0]: VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0)
12.3.2.2
AVTCH - VLAN Type Code Register High
IC Address 029; CPU Address:h101 Accessed by CPU and IC (R/W) Bit[7:0]: VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 0x81)
12.3.2.3
PVMAP00_0 - Port 0 Configuration Register 0
IC Address 02A, CPU Address:h102 Accessed by CPU and IC (R/W) In Port Based VLAN Mode Bit[7:0]: VLAN Mask for port 0 (Default 0xFF)
This register indicates the legal egress ports. A "1" on bit 7 means that the packet can be sent to port 7. A "0" on bit 7 means that any packet destined to port 7 will be discarded. This register works with registers 1 to form a 10 bit mask to all egress ports.
57
Zarlink Semiconductor Inc.
ZL50404
12.3.2.4 PVMAP00_1 - Port 0 Configuration Register 1
IC Address h34, CPU Address:h103 Accessed by CPU and IC (R/W) In Port based VLAN Mode Bit[1:0]: Bit[7:2]: VLAN Mask for ports 9 to 8 (Default 0x3) Reserved (Default 0x3F)
Data Sheet
12.3.2.5
PVMAP00_3 - Port 0 Configuration Register 3
IC Address h3E, CPU Address:h105 Accessed by CPU and IC (R/W) In Port Based VLAN Mode Bit [2:0]: Bit [5:3]: Reserved Default Transmit priority. Used when Bit[7]=1 (Default 0) Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 Transmit Priority Level 2 Transmit Priority Level 3 (Highest) Bit [6]: Default Discard priority. Used when Bit[7]=1 0 - Discard Priority Level 0 (Lowest) (Default) 1 - Discard Priority Level 1(Highest) Enable Fix Priority (Default 0) 0 - Disable. All frames are analysed. Transmit Priority and Discard Priority are based on VLAN Tag, TOS or Logical Port. 1 - Enable. Transmit Priority and Discard Priority are based on values programmed in bit [6:3]
Bit [7]:
12.3.2.6
PVMAPnn_0,1,3 - Ports 1~3,8,9 Configuration Registers
PVMAP01_0,1,3 IC Address h2B,35,3F; CPU Address:h106,107,109 (Port 1) PVMAP02_0,1,3 IC Address h2C,36,40; CPU Address:h10A, 10B, 10D (Port 2) PVMAP03_0,1,3 IC Address h2D,37,41; CPU Address:h10E, 10F, 111 (Port 3) PVMAP08_0,1,3 IC Address h32,3C,46; CPU Address:h122, 123, 125 (Port CPU) PVMAP09_0,1,3 IC Address h33,3D,47; CPU Address:h126, 127, 129 (Port MMAC)
12.3.2.7
PVMODE
IC Address: h048, CPU Address:h170 Accessed by CPU and IC (R/W) Bit [0]: Reserved. Must be 0.
58
Zarlink Semiconductor Inc.
ZL50404
Bit [1]: Slow learning (Default = 0)
Data Sheet
Same function as SE_OP MODE bit[7]. Either bit can enable the function; both need to be turned off to disable the feature. Bit [2]: Disable dropping frames with destination MAC addresses 0180C2000001 to 0180C200000F 0: Drop all frames in the range (Default) 1: Treats frames as multicast Flooding control in secure mode 0: Enable - Learning disabled port will not receive any flooding packets (Default) 1: Disable Support MAC address 0 0: MAC address 0 is not learned. (Default) 1: MAC address 0 is learned. Disable spanning tree packet to CPU in managed mode 1: Received spanning tree packet is forwarded as multicast. 0: Received spanning tree packet is forwarded to CPU. (Default) Reserved. Must be 0. Enable logical port match in secure mode 0: Disable (Default) 1: Enable - When Well Known or User Define logical port force discard enabled, force any IP packet with logical port number matching logical port numbers to CPU.
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]: Bit [7]:
12.3.3
(Group 2 Address) Port Trunking Groups
Trunk Group - Up to four RMAC ports can be selected for each trunk group.
12.3.3.1
TRUNKn- Trunk Group 0~7
CPU Address:h200+N (N = trunk group) Accessed by CPU (R/W) Bit [3:0] Port 3-0 bit map of trunk N. (Default 0) B i t 3 TRUNK0 P o r t 3 P o r t 0 B i t 0
59
Zarlink Semiconductor Inc.
ZL50404
12.3.3.2
CPU Address:h208+4xN (N = trunk group) Accessed by CPU (R/W) Bit [3:0] Bit [7:4] Hash result 0 destination port number (Default 0) Hash result 1 destination port number (Default 0)
Data Sheet
TRUNKn_HASH10 - Trunk group 0~7 hash result 1/0 destination port number
12.3.3.3
TRUNKn_HASH32 - Trunk group 0~7 hash result 3/2 destination port number
CPU Address:h209+4xN (N = trunk group) Accessed by CPU (R/W) Bit [3:0] Bit [7:4] Hash result 2 destination port number (Default 0) Hash result 3 destination port number (Default 0)
12.3.3.4
TRUNKn_HASH54 - Trunk group 0~7 hash result 5/4 destination port number
CPU Address:h20A+4xN (N = trunk group) Accessed by CPU (R/W) Bit [3:0] Bit [7:4] Hash result 4 destination port number (Default 0) Hash result 5 destination port number (Default 0)
12.3.3.5
TRUNKn_HASH76 - Trunk group 0~7 hash result 7/6 destination port number
CPU Address:h20B+4xN (N = trunk group) Accessed by CPU (R/W) Bit [3:0] Bit [7:4] Hash result 6 destination port number (Default 0) Hash result 7 destination port number (Default 0)
60
Zarlink Semiconductor Inc.
ZL50404
Multicast Hash Registers
Data Sheet
Multicast Hash registers are used to distribute multicast traffic. 16 registers are used to form a 8-entry array; each entry has 6 bits, with each bit representing one port. Any port not belonging to a trunk group should be programmed with 1. Ports belonging to the same trunk group should only have a single port set to "1" per entry. The port set to "1" is picked to transmit the multicast frame when the hash value is met. Hash Value =0 Hash Value =1 Hash Value =2 Hash Value =3 Hash Value =4 Hash Value =5 Hash Value =6 Hash Value =7 HASH0-1 HASH1-1 HASH2-1 HASH3-1 HASH4-1 HASH5-1 HASH6-1 HASH7-1 P o r t 9 P o r t 8 HASH0-0 HASH1-0 HASH2-0 HASH3-0 HASH4-0 HASH5-0 HASH6-0 HASH7-0 P o r t 3 P o r t 0
12.3.3.6
MULTICAST_HASHn-0 - Multicast hash result 0~7 mask byte 0
CPU Address:h228+2xN (N = hash value) Accessed by CPU (R/W) Bit[3:0]: Bit[7:4]: Port 3-0 bit map for multicast hash. (Default 0xF) Reserved. (Default 0xF)
12.3.3.7
MULTICAST_HASHn-1 - Multicast hash result 0~7 mask byte 1
CPU Address:h229+2xN (N = hash value) Accessed by CPU (R/W) Bit[1:0]: Bit[5:2]: Bit[7:6]: Port 9-8 bit map for multicast hash. (Default 0x3) Reserved (Default 0xF) MULTICAST_HASH0-1 Hash Select. The hash algorithm selected is valid for all trunks (Default 00) 00 - Use Source and Destination Mac Address for hashing 01 - Use Source Mac Address for hashing 10 - Use Destination Mac Address for hashing 11 - Use Source Port Number for hashing MULTICAST_HASH[7:1]-1 Reserved (Default 0x3)
61
Zarlink Semiconductor Inc.
ZL50404
12.3.4 (Group 3 Address) CPU Port Configuration Group
5 MAC5 MAC4 MAC3 MAC2 MAC1 MAC0 0 (MC bit)
Data Sheet
MAC5 to MAC0 registers form the CPU MAC address. When a packet with destination MAC address match MAC [5:0], the packet is forwarded to the CPU.
12.3.4.1
MAC0 - CPU Mac address byte 0
CPU Address:h300 Accessed by CPU (R/W) Bit[7:0]: Byte 0 of the CPU MAC address (Default 0)
12.3.4.2
MAC1 - CPU Mac address byte 1
CPU Address:h301 Accessed by CPU (R/W) Bit[7:0]: Byte 1 of the CPU MAC address (Default 0)
12.3.4.3
MAC2 - CPU Mac address byte 2
CPU Address:h302 Accessed by CPU (R/W) Bit[7:0]: Byte 2 of the CPU MAC address (Default 0)
12.3.4.4
MAC3 - CPU Mac address byte 3
CPU Address:h303 Accessed by CPU (R/W) Bit[7:0]: Byte 3 of the CPU MAC address (Default 0)
12.3.4.5
MAC4 - CPU Mac address byte 4
CPU Address:h304 Accessed by CPU (R/W) Bit[7:0]: Byte 4 of the CPU MAC address (Default 0)
62
Zarlink Semiconductor Inc.
ZL50404
12.3.4.6 MAC5 - CPU Mac address byte 5
CPU Address:h305 Accessed by CPU (R/W) Bit[7:0]: Byte 5 of the CPU MAC address (Default 0)
Data Sheet
12.3.4.7
INT_MASK0 - Interrupt Mask
CPU Address:h306 Accessed by CPU (R/W) The CPU can dynamically mask the interrupt when it is busy and doesn't want to be interrupted. (Default 0xFF) 1: Mask the interrupt 0: Unmask the interrupt (Enable interrupt) CPU frame interrupt. CPU frame buffer has data for CPU to read Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read Reserved Device Timeout Detected interrupt
Bit [0]: Bit [1]: Bit [2]: Bit [6:3]: Bit [7]
12.3.4.8
INTP_MASK0 - Interrupt Mask for MAC Port 0,1
CPU Address:h310 Accessed by CPU (R/W) The CPU can dynamically mask the interrupt when it is busy and doesn't want to be interrupted (Default 0xFF) 1: Mask the interrupt 0: Unmask the interrupt Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a statistic counter wraps around. Refer to hardware statistic counter for interrupt sources Port 0 link change mask Port 0 module detect mask Reserved Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic counter wraps around. Refer to hardware statistic counter for interrupt sources. Port 1 link change mask Port 1 module detect mask Reserved
Bit [0]: Bit [1]: Bit [2:] Bit [3:] Bit [4]: Bit [5]: Bit [6]: Bit [7]:
63
Zarlink Semiconductor Inc.
ZL50404
12.3.4.9 INTP_MASKn - Interrupt Mask for MAC Ports Registers
INTP_MASK1 CPU Address:h311 (Ports 2,3) INTP_MASK4 CPU Address:h314 (Port CPU,MMAC)
Data Sheet
12.3.4.10
RQS - Receive Queue Select
CPU Address:h323 Accessed by CPU (RW) Select which receive queue is used. Bit [0]: Bit [1]: Bit[2]: Bit[3]: Bit[4]: Bit[5]: Bit[6]: Bit[7]: Select Queue 0 Select Queue 1 Select Queue 2 Select Queue 3 Select Multicast Queue 0 Select Multicast Queue 1 Select Multicast Queue 2 Select Multicast Queue 3
Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0).
12.3.4.11
RQSS - Receive Queue Status
CPU Address:h324 Accessed by CPU (RO) CPU receive queue status Bit[3:0]: Bit[7:4]: Unicast Queue 3 to 0 not empty Multicast Queue 3 to 0 not empty
12.3.4.12
MAC01 - Increment MAC port 0,1 address
CPU Address:h325 Accessed by CPU (RW) Bit[2:0]: Bit[3]: Bit[6:4]: Bit[7]: Bit[42:40] of Port 0 MAC address Reserved Bit [42:40] of Port 1 MAC address Reserved
64
Zarlink Semiconductor Inc.
ZL50404
12.3.4.13 MAC23 - Increment MAC port 2,3 address
CPU Address:h326 Accessed by CPU (RW) Bit[2:0]: Bit[3]: Bit[6:4]: Bit[7]: Bit [42:40] of Port 2 MAC address Reserved Bit [42:40] of Port 3 MAC address Reserved
Data Sheet
12.3.4.14
MAC9 -Increment MAC port 9 address
CPU Address:h329 Accessed by CPU (RW) Bit[7:0]: Bit[47:40] of Port 9 MAC address
12.3.5 12.3.5.1
(Group 4 Address) Search Engine Group AGETIME_LOW - MAC address aging time Low
IC Address h049; CPU Address:h400 Accessed by CPU and IC (R/W) Used in conjuction with AGETIME_HIGH. The ZL50404 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bit[7:0]: Low byte of the MAC address aging timer (Default 0x5C)
12.3.5.2
AGETIME_HIGH -MAC address aging time High
IC Address h04A; CPU Address h401 Accessed by CPU and IC (R/W) Bit[7:0]: High byte of the MAC address aging timer (Default 0)
The default setting of AGETIME_LOW/HIGH provides 300 seconds aging time. Aging time is based on the following equation: {AGETIME_HIGH,AGETIME_LOW} X (# of MAC entries in the memory X 800sec). Number of MAC entries = 4K.
65
Zarlink Semiconductor Inc.
ZL50404
12.3.5.3 SE_OPMODE - Search Engine Operation Mode
CPU Address:h403 Accessed by CPU (R/W) Note: ECR2[2] enable/disable learning for each port. Bit [0]: Bit [1]: Reserved. Must be 0. Protocol filtering mode 0 - Inclusive (Default) 1 - Exclusive
Data Sheet
Bit [2]:
Report control 1 - Disable report MAC address deletion 0 - Report MAC address deletion (MAC address is deleted from MCT after aging time) (Default) Delete Control 1 - Disable aging logic from removing MAC during aging 0 - MAC address entry is removed when it is old enough to be aged (Default) However, a report is still sent to the CPU in both cases, when bit[2] = 0
Bit [3]:
Bit [4]: Bit [5] Bit [6]:
Reserved 1 - Report ARP packet to CPU 0 - No ARP packet reporting (Default) Disable MCT speed-up aging 1 - Disable speed-up aging when MCT resource is low. 0 - Enable speed-up aging when MCT resource is low. (Default) Slow Learning 1- Enable slow learning. Learning is temporary disabled when search demand is high 0 - Learning is performed independent of search demand (Default)
Bit [7]:
66
Zarlink Semiconductor Inc.
ZL50404
12.3.6 12.3.6.1 (Group 5 Address) Buffer Control/QOS Group QOSC - QOS Control
Data Sheet
IC Address h04B; CPU Address:h500 Accessed by CPU and I2C (R/W) Bit [0]: Enable TX rate control (on RMAC ports only) 1 - Enable 0 - Disable (Default) Enable RX rate control (on RMAC ports only) 1 - Enable 0 - Disable (Default) Reserved Select VLAN tag or TOS (IP packets) to be preferentially picked to map transmit priority and drop priority 0 - Select VLAN Tag priority field over TOS (Default) 1 - Select TOS over VLAN tag priority field Select TOS bits for Priority 0 - Use TOS [4:2] bits to map the transmit priority (Default) 1 - Use TOS [7:5] bits to map the transmit priority Select TOS bits for Drop priority 0 - Use TOS [4:2] bits to map the drop priority (Default) 1 - Use TOS [7:5] bits to map the drop priority
Bit [1]:
Bit [4:2]: Bit [5]:
Bit [6]:
Bit [7]:
12.3.6.2
2
UCC - Unicast Congestion Control
I C Address h068, CPU Address: 510 Accessed by CPU and I2C (R/W) Bit [7:0]: Number of frame count. Used for best effort dropping at B% when destination port's best effort queue reaches UCC threshold and shared pool is all in use. Granularity is 16 granule (Default 0x6)
12.3.6.3
MCC - Multicast Congestion Control
IC Address h069, CPU Address: 511 Accessed by CPU and IC (R/W) Bit [7:0]: In multiples of 16 granules (granularity). Used for triggering MC flow control when destination port's multicast best effort queue reaches MCC threshold. (Default 0x6)
67
Zarlink Semiconductor Inc.
ZL50404
12.3.6.4 MCCTH - Multicast Threshold Control
CPU Address: 512 Accessed by CPU (R/W) Bit [7:0]:
Data Sheet
Threshold on the multicast granule count. Exceeding the threshold consider as multicast resource low and the new multicast will be dropped at B% or flow control is triggered if enabled. (Default: 0x3)
12.3.6.5
RDRC0 - WRED Rate Control 0
IC Address 090, CPU Address 513 Accessed by CPU and I2C (R/W) Bits[3:0]: Bits[7:4]: Corresponds to the frame drop percentage Y% for WRED. Granularity 6.25%. Corresponds to the frame drop percentage X% for WRED. Granularity 6.25%.
See Programming QoS Registers application note for more information
12.3.6.6
RDRC1 - WRED Rate Control 1
IC Address 091, CPU Address 514 Accessed by CPU and IC (R/W) Bits[3:0]: Bits[7:4]: Corresponds to the best effort frame drop percentage B%, when shared pool is all in use and destination port best effort queue reaches UCC. Granularity 6.25%. Corresponds to the frame drop percentage Z% for WRED. Granularity 6.25%.
See Programming QoS Registers application note for more information
12.3.6.7
RDRC2 - WRED Rate Control 2
CPU Address 515 Accessed by CPU (R/W) Bits[3:0]: Bits[7:4]: Corresponds to the frame drop percentage RB%, for rate control. Granularity 6.25%. Corresponds to the frame drop percentage RA% for rate control. Granularity 6.25%.
12.3.6.8
SFCB - Share FCB Size
IC Address h074, CPU Address 518 Accessed by CPU and IC (R/W) Bits [7:0]: Expressed in multiples of 16 granules. Buffer reservation for shared pool.
68
Zarlink Semiconductor Inc.
ZL50404
12.3.6.9 C1RS - Class 1 Reserve Size
IC Address h075, CPU Address 519 Accessed by CPU and IC (R/W) Bits [7:0]: Class 1 FCB Reservation
Data Sheet
Buffer reservation for class 1. Granularity 16 granules. (Default 0)
12.3.6.10
C2RS - Class 2 Reserve Size
IC Address h076, CPU Address 51A Accessed by CPU and IC (R/W) Bits [7:0]: Class 2 FCB Reservation
Buffer reservation for class 2. Granularity 16 granules. (Default 0)
12.3.6.11
C3RS - Class 3 Reserve Size
IC Address h077, CPU Address 51B Accessed by CPU and IC (R/W) Bits [7:0]: Class 3 FCB Reservation
Buffer reservation for class 3. Granularity 16 granules. (Default 0)
12.3.6.12
AVPML - VLAN Tag Priority Map
IC Address h056; CPU Address:h530 Accessed by CPU and IC (R/W) Registers AVPML, AVPMM, and AVPMH allow the eight VLAN Tag priorities to map into eight Internal level transmit priorities. Under the Internal transmit priority, seven is the highest priority where as zero is the lowest. This feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used inside the 2604. When the packet goes out it carries the original priority. Bit [2:0]: Bit [5:3]: Bit [7:6]: Priority when the VLAN tag priority field is 0 (Default 0) Priority when the VLAN tag priority field is 1 (Default 0) Priority when the VLAN tag priority field is 2 (Default 0)
69
Zarlink Semiconductor Inc.
ZL50404
12.3.6.13 AVPMM - VLAN Priority Map
IC Address h057, CPU Address:h531 Accessed by CPU and IC (R/W) Map VLAN priority into eight level transmit priorities: Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: Priority when the VLAN tag priority field is 2 (Default 0) Priority when the VLAN tag priority field is 3 (Default 0) Priority when the VLAN tag priority field is 4 (Default 0) Priority when the VLAN tag priority field is 5 (Default 0)
Data Sheet
12.3.6.14
AVPMH - VLAN Priority Map
IC Address h058, CPU Address:h532 Accessed by CPU and IC (R/W) Map VLAN priority into eight level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: Priority when the VLAN tag priority field is 5 (Default 0) Priority when the VLAN tag priority field is 6 (Default 0) Priority when the VLAN tag priority field is 7 (Default 0)
12.3.6.15
AVDM - VLAN Discard Map
IC Address h05C, CPU Address:h533 Accessed by CPU and IC (R/W) Map VLAN priority into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Frame drop priority when VLAN Tag priority field is 0 (Default 0) Frame drop priority when VLAN Tag priority field is 1 (Default 0) Frame drop priority when VLAN Tag priority field is 2 (Default 0) Frame drop priority when VLAN Tag priority field is 3 (Default 0) Frame drop priority when VLAN Tag priority field is 4 (Default 0) Frame drop priority when VLAN Tag priority field is 5 (Default 0) Frame drop priority when VLAN Tag priority field is 6 (Default 0) Frame drop priority when VLAN Tag priority field is 7 (Default 0)
70
Zarlink Semiconductor Inc.
ZL50404
12.3.6.16 TOSPML - TOS Priority Map
IC Address h059, CPU Address:h540 Accessed by CPU and IC (R/W) Map TOS field in IP packet into eight level transmit priorities Bit [2:0]: Bit [5:3]: Bit [7:6]: Priority when the TOS field is 0 (Default 0) Priority when the TOS field is 1 (Default 0) Priority when the TOS field is 2 (Default 0)
Data Sheet
12.3.6.17
TOSPMM - TOS Priority Map
IC Address h05A, CPU Address:h541 Accessed by CPU and IC (R/W) Map TOS field in IP packet into eight level transmit priorities Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: Priority when the TOS field is 2 (Default 0) Priority when the TOS field is 3 (Default 0) Priority when the TOS field is 4 (Default 0) Priority when the TOS field is 5 (Default 0)
12.3.6.18
TOSPMH - TOS Priority Map
IC Address h05B, CPU Address:h542 Accessed by CPU and IC (R/W) Map TOS field in IP packet into eight level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: Priority when the TOS field is 5 (Default 0) Priority when the TOS field is 6 (Default 0) Priority when the TOS field is 7 (Default 0)
12.3.6.19
TOSDML - TOS Discard Map
IC Address h05D, CPU Address:h543 Accessed by CPU and IC (R/W) Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Frame drop priority when TOS field is 0 (Default 0) Frame drop priority when TOS field is 1 (Default 0) Frame drop priority when TOS field is 2 (Default 0)
71
Zarlink Semiconductor Inc.
ZL50404
Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Frame drop priority when TOS field is 3 (Default 0) Frame drop priority when TOS field is 4 (Default 0) Frame drop priority when TOS field is 5 (Default 0) Frame drop priority when TOS field is 6 (Default 0) Frame drop priority when TOS field is 7 (Default 0)
Data Sheet
12.3.6.20
USER_PROTOCOL_[7:0] - User Define Protocol 0~7
IC Address h0B3-0BA, CPU Address:h550-557 Accessed by CPU and IC (R/W) (Default 00) This register is duplicated eight times from PROTOCOL 0~7 and allows the CPU to define eight separate protocols. Bits[7:0]: User Define Protocol
12.3.6.21 Discard
USER_PROTOCOL_FORCE_DISCARD[7:0] - User Define Protocol 0~7 Force
IC Address h0BB, CPU Address 558 Accessed by CPU and IC (R/W) Bits[0]: Enable Protocol 0 Force Discard 1 - Enable 0 - Disable Enable Protocol 1 Force Discard Enable Protocol 2 Force Discard Enable Protocol 3 Force Discard Enable Protocol 4 Force Discard Enable Protocol 5 Force Discard Enable Protocol 6 Force Discard Enable Protocol 7 Force Discard
Bits[1]: Bits[2]: Bits[3]: Bits[4]: Bits[5]: Bits[6]: Bits[7]:
72
Zarlink Semiconductor Inc.
ZL50404
User Defined Logical Ports and Well Known Ports
Data Sheet
The ZL50404 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: * * * * * * * * 23 512 6000 443 111 22555 22 554
Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_ Enable can individually turn on/off each Well Known Port if desired. Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7 registers. Two registers are required to be programmed for the logical port number. The respective priority can be programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via User_Port_Enable register. The User Defined Range provides a range of logical port numbers with the same priority level. Programming is similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the upper limit and more than the lower limit will use the priority specified in RPRIORITY.
12.3.6.22
WELL_KNOWN_PORT[1:0]_PRIORITY- Well Known Logic Port 1 and 0 Priority
IC Address h0A8, CPU Address 560 Accessed by CPU and IC (R/W) Bits[3:0]: Bits[7:4]: Priority setting, transmission + dropping, for Well known port 0 (23 for telnet) Priority setting, transmission + dropping, for Well known port 1 (512 for TCP/UDP)
12.3.6.23
WELL_KNOWN_PORT[3:2]_PRIORITY- Well Known Logic Port 3 and 2 Priority
IC Address h0A9, CPU Address 561 Accessed by CPU and IC (R/W) Bits[3:0]: Bits[7:4]: Priority setting, transmission + dropping, for Well known port 2 (6000 for XWIN) Priority setting, transmission + dropping, for Well known port 3 (443 for HTTP sec)
73
Zarlink Semiconductor Inc.
ZL50404
12.3.6.24
IC Address h0AA, CPU Address 562 Accessed by CPU and IC (R/W) Bits[3:0]: Bits[7:4]:
Data Sheet
WELL_KNOWN_PORT[5:4]_PRIORITY- Well Known Logic Port 5 and 4 Priority
Priority setting, transmission + dropping, for Well known port 4 (111 for sun remote procedure call) Priority setting, transmission + dropping, for Well known port 5 (22555 for IP Phone call setup)
12.3.6.25
WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority
IC Address h0AB, CPU Address 563 Accessed by CPU and IC (R/W) Bits[3:0]: Bits[7:4]: Priority setting, transmission + dropping, for Well known port 6 (22 for ssh) Priority setting, transmission + dropping, for Well known port 7 (554 for rtsp)
12.3.6.26
WELL_KNOWN_PORT_ENABLE[7:0] - Well Known Logic Port 0 to 7 Enables
IC Address h0AC, CPU Address 564 Accessed by CPU and IC (R/W) Bits[0]: Enable Well Known Port 0 Priority 1 - Enable 0 - Disable Enable Well Known Port 1 Priority Enable Well Known Port 2 Priority Enable Well Known Port 3 Priority Enable Well Known Port 4 Priority Enable Well Known Port 5 Priority Enable Well Known Port 6 Priority Enable Well Known Port 7 Priority
Bits[1]: Bits[2]: Bits[3]: Bits[4]: Bits[5]: Bits[6]: Bits[7]:
12.3.6.27 Discard
WELL_KNOWN_PORT_FORCE_DISCARD[7:0] - Well Known Logic Port 0~7 Force
IC Address h0AD, CPU Address 565 Accessed by CPU and IC (R/W) Bits[0]: Enable Well Known Port 0 Force Discard 1 - Enable 0 - Disable
74
Zarlink Semiconductor Inc.
ZL50404
Bits[1]: Bits[2]: Bits[3]: Bits[4]: Bits[5]: Bits[6]: Bits[7]: Enable Well Known Port 1 Force Discard Enable Well Known Port 2 Force Discard Enable Well Known Port 3 Force Discard Enable Well Known Port 4 Force Discard Enable Well Known Port 5 Force Discard Enable Well Known Port 6 Force Discard Enable Well Known Port 7 Force Discard
Data Sheet
12.3.6.28
USER_PORT[7:0]_[LOW/HIGH] - User Define Logical Port 0~7
IC Address h092-099(Low); CPU Address 570+2xN(Low) (N = logical port number) IC Address h09A-0A1(High); CPU Address 571+2xN(High) Accessed by CPU and IC (R/W) (Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define eight separate ports. 7 TCP/UDP Logic Port Low 7 TCP/UDP Logic Port High 0 0
12.3.6.29
USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
IC Address h0A2, CPU Address 590 Accessed by CPU and IC (R/W) The chip allows the CPU to define the priority Bits[3:0]: Bits[7:4]: Priority setting, transmission + dropping, for logic port 0 Priority setting, transmission + dropping, for logic port 1 (Default 00)
12.3.6.30
USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
IC Address h0A3, CPU Address 591 Accessed by CPU and IC (R/W) Bits[3:0]: Bits[7:4]: Priority setting, transmission + dropping, for logic port 2 Priority setting, transmission + dropping, for logic port 3 (Default 00)
75
Zarlink Semiconductor Inc.
ZL50404
12.3.6.31 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority
IC Address h0A4, CPU Address 592 Accessed by CPU and IC (R/W) Bits[3:0]: Bits[7:4]: Priority setting, transmission + dropping, for logic port 4 Priority setting, transmission + dropping, for logic port 5 (Default 00)
Data Sheet
12.3.6.32
USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority
IC Address h0A5, CPU Address 593 Accessed by CPU and IC (R/W) Bits[3:0]: Bits[7:4]: Priority setting, transmission + dropping, for logic port 6 Priority setting, transmission + dropping, for logic port 7 (Default 00)
12.3.6.33
USER_PORT_ENABLE[7:0] - User Define Logic Port 0 to 7 Enables
IC Address h0A6, CPU Address 594 Accessed by CPU and IC (R/W) Bits[0]: Enable User Port 0 Priority 1 - Enable 0 - Disable Enable User Port 1 Priority Enable User Port 2 Priority Enable User Port 3 Priority Enable User Port 4 Priority Enable User Port 5 Priority Enable User Port 6 Priority Enable User Port 7 Priority
Bits[1]: Bits[2]: Bits[3]: Bits[4]: Bits[5]: Bits[6]: Bits[7]:
12.3.6.34
USER_PORT_FORCE_DISCARD[7:0] - User Define Logic Port 0~7 Force Discard
IC Address h0A7, CPU Address 595 Accessed by CPU and IC (R/W) Bits[0]: Enable User Port 0 Force Discard 1 - Enable 0 - Disable Enable User Port 1 Force Discard Enable User Port 2 Force Discard
Bits[1]: Bits[2]:
76
Zarlink Semiconductor Inc.
ZL50404
Bits[3]: Bits[4]: Bits[5]: Bits[6]: Bits[7]: Enable User Port 3 Force Discard Enable User Port 4 Force Discard Enable User Port 5 Force Discard Enable User Port 6 Force Discard Enable User Port 7 Force Discard
Data Sheet
12.3.6.35
RLOWL - User Define Range Low Bit 7:0
IC Address h0AE, CPU Address: 5A0 Accessed by CPU and IC (R/W) Bits[7:0]: Lower 8 bit of the User Define Logical Port Low Range
12.3.6.36
RLOWH - User Define Range Low Bit 15:8
IC Address h0AF, CPU Address: 5A1 Accessed by CPU and IC (R/W) Bits[7:0]: Upper 8 bit of the User Define Logical Port Low Range
12.3.6.37
RHIGHL - User Define Range High Bit 7:0
IC Address h0B0, CPU Address: 5A2 Accessed by CPU and IC (R/W) Bits[7:0]: Lower 8 bit of the User Define Logical Port High Range
12.3.6.38
RHIGHH - User Define Range High Bit 15:8
IC Address h0B1, CPU Address: 5A3 Accessed by CPU and IC (R/W) Bits[7:0]: Upper 8 bit of the User Define Logical Port High Range
12.3.6.39
RPRIORITY - User Define Range Priority
IC Address h0B2, CPU Address: 5A4 Accessed by CPU and IC (R/W) RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bits[0]: Bit[3:1] Drop Priority (inclusive only) Transmit Priority (inclusive only)
77
Zarlink Semiconductor Inc.
ZL50404
Bit[5:4] Bit[7:6] Reserved 00 - No Filtering 01 - Exclusive Filtering (x<=RLOW or x>=RHIGH) 10 - Inclusive Filtering (RLOWData Sheet
12.3.7 12.3.7.1
(Group 6 Address) MISC Group MII_OP0 - MII Register Option 0
IC Address 0BC, CPU Address:h600 Accessed by CPU and IC (R/W) Bit[4:0]: Bit[6:5] Bits [7]: Vendor specified link status register address (null value means don't use it) (Default 00). This is used if the Linkup bit position in the PHY is non-standard Reserved Half duplex flow control feature 0 = Half duplex flow control always enable 1 = Half duplex flow control by negotiation
12.3.7.2
MII_OP1 - MII Register Option 1
IC Address 0BD, CPU Address:h601 Accessed by CPU and IC (R/W) Bits[3:0]: Bits[7:4]: Duplex bit location in vendor specified register Speed bit location in vendor specified register (Default 00)
12.3.7.3
FEN - Feature Register
IC Address 0BE, CPU Address:h602) Accessed by CPU and IC (R/W) Bits [0]: Statistic Counter 0 - Disable (Default) 1 - Enable (all ports) When statistic counter is enable, an interrupt control frame is generated to the CPU, every time a counter wraps around. This feature requires an external CPU. Bits[1]: Bit [2]: Reserved Support DS EF Code. 0 - Disable (Default) 1 - Enable (all ports) When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for 110 and drop is set for 0.
78
Zarlink Semiconductor Inc.
ZL50404
Bit [3]: Bit [4]: Bit [5]: Reserved. Must be 0. Reserved. Must be 1. Report to CPU 0 - Disable (Default) 1 - Enable
Data Sheet
When disable new VLAN port association report, new MAC address report or aging reports are disable for all ports. When enable, register SE_OPEMODE is used to enable/disable selectively each function. Bit [6]: MII Management State Machine 0: Enable (Default) 1: Disable This bit must be set so that there is no contention on the MDIO bus between MII Managment state machine and MIIC & MIID PHY register accesses. MCT Link List structure 0 - Enable (Default) 1 - Disable
Bit [7]:
12.3.7.4
MIIC0 - MII Command Register 0
CPU Address:h603 Accessed by CPU (R/W) Bits[7:0]: MII Command Data [7:0]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command.
12.3.7.5
MIIC1 - MII Command Register 1
CPU Address:h604 Accessed by CPU (R/W) Bits[7:0]: MII Command Data [15:8]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command.
79
Zarlink Semiconductor Inc.
ZL50404
12.3.7.6 MIIC2 - MII Command Register 2
CPU Address:h605 Accessed by CPU (R/W) Bit [4:0] Bit [6:5] Bit [7] REG_AD - Register PHY Address OP - Operation code "10" for read command and "01" for write command Reserved
Data Sheet
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command.
12.3.7.7
MIIC3 - MII Command Register 3
CPU Address:h606 Accessed by CPU (R/W) Bits [4:0] Bit [5] Bit [6] Bit [7] PHY_AD - 5 Bit PHY Address Reserved VALID - Data Valid from PHY (Read Only) RDY - Data is returned from PHY (Read Only)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. Writing this register will initiate a serial management cycle to the MII management interface.
12.3.7.8
MIID0 - MII Data Register 0
CPU Address:h607 Accessed by CPU (RO) Bits[7:0]: MII Data [7:0]
12.3.7.9
MIID1 - MII Data Register 1
CPU Address:h608 Accessed by CPU (RO) Bits[7:0]: MII Data [15:8]
80
Zarlink Semiconductor Inc.
ZL50404
12.3.7.10 USD - One Micro Second Divider
CPU Address:h609 Accessed by CPU (R/W) Bits[5:0]:
Data Sheet
Divider to get one micro second from M_CLK (only used when not in standard RMII mode) In a MII or GPSI system, a 50MHz M_CLK may not be available. The system designer can decide to use another frequency on the M_CLK signal. To compensate for this, this register is required to be programmed. For example. If 20MHz is used on M_CLK, to compensate for the difference, this register is programmed with 20 to provide 1usec for internal reference. Reserved
Bits[7:6]:
12.3.7.11
DEVICE Mode
CPU Address:h60A Accessed by CPU (R/W) Bit[0]: Bit[1]: Reserved CPU Interrupt Polarity 0: Negative Polarity 1: Positive Polarity (Default) Reserved DEVICE ID (Default 0). This is for stacking operation. This is the stack ID for loop topology.
Bit[4:2]: Bit [7:5]:
12.3.7.12
CHECKSUM - EEPROM Checksum
IC Address 0FF, CPU Address:h60B Accessed by CPU and IC (R/W) Bit [7:0]: Checksum content (Default 0)
This register is used in unmanaged mode only. Before requesting that the ZL50404 updates the EEPROM device, the correct checksum needs to be calculated and written into this checksum register. The checksum formula is:
FF
S
i=0
IC register = 0
When the ZL50404 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50404 does not start and pin CHECKSUM_OK is set to zero.
81
Zarlink Semiconductor Inc.
ZL50404
12.3.7.13 LHBTimer - Link Heart Beat Timeout Timer
CPU Address:h610 Accessed by CPU (R/W)
Data Sheet
In slot time (512 bit time). LHB packet will be sent out to the remote device if no other packet is transmitted in this period. The receiver will trigger LHB timeout interrupt if not receiving any good packet in two of this period.
12.3.7.14
LHBReg0, LHBReg1 - Link Heart Beat OpCode
CPU Address:h611, h612 Accessed by CPU (R/W) The LHB frame uses MAC control frame format (same as flow control frame.) The register here defines the operation code. (flow control frame has h0001).
12.3.7.15
fMACCReg0, fMACCReg1 - MAC Control Frame OpCode
CPU Address:h613, h614 Accessed by CPU (R/W) The registers define the operation code if MAC control frame is forced out by processor.
12.3.7.16
FCB Base Address Register 0
IC Address 0BF, CPU Address:h620 Accessed by CPU and IC (R/W) Bit [7:0] FCB Base address bit 7:0 (Default 0)
12.3.7.17
FCB Base Address Register 1
IC Address 0C0, CPU Address:h621 Accessed by CPU and IC (R/W) Bit [7:0] FCB Base address bit 15:8 (Default 0x60)
12.3.7.18
FCB Base Address Register 2
IC Address 0C1, CPU Address:h622 Accessed by CPU and IC (R/W) Bit [7:0] FCB Base address bit 23:16 (Default 0)
82
Zarlink Semiconductor Inc.
ZL50404
12.3.8 12.3.8.1 (Group 7 Address) Port Mirroring Group MIRROR CONTROL - Port Mirror Control Register
Data Sheet
CPU Address 70C Accessed by CPU (R/W) (Default 00) Bit [3:0]: Bit[4] Bit[5] Bit [6]: Bit [7]: Destination port to be mirrored to. Mirror Flow from MIRROR_SRC_MAC[5:0] to MIRROR_DEST_MAC[5:0] Mirror Flow from MIRROR_DEST_MAC[5:0] to MIRROR_SRC_MAC[5:0] Mirror when address is destination Mirror when address is source
12.3.8.2
MIRROR_DEST_MAC[5:0] - Mirror Destination Mac Address 0~5
CPU Address 700-705 Accessed by CPU (R/W) DEST_MAC5 [47:40] (Default 00) DEST_MAC4 [39:32] (Default 00) DEST_MAC3 [31:24] (Default 00) DEST_MAC2 [23:16] (Default 00) DEST_MAC1 [15:8] (Default 00) DEST_MAC0 [7:0] (Default 00)
12.3.8.3
MIRROR_SRC _MAC[5:0] - Mirror Destination Mac Address 0~5
CPU Address 706-70B Accessed by CPU (R/W) SRC_MAC5 [47:40] (Default 00) SRC_MAC4 [39:32] (Default 00) SRC_MAC3 [31:24] (Default 00) SRC_MAC2 [23:16] (Default 00) SRC_MAC1 [15:8] (Default 00) SRC_MAC0 [7:0] (Default 00)
12.3.8.4
RMAC_MIRROR0 - RMAC Mirror 0
CPU Address 710 Accessed by CPU (R/W) Bit [2:0]: Bit [3]: Source port to be mirrored Mirror path 0: Receive 1: Transmit Destination port for mirrored traffic Mirror enable
Bit [6:4]: Bit [7]:
83
Zarlink Semiconductor Inc.
ZL50404
12.3.8.5 RMAC_MIRROR1 - RMAC Mirror 1
CPU Address 711 Accessed by CPU (R/W) Bit [2:0]: Bit [3]: Source port to be mirrored Mirror path 0: Receive 1: Transmit Destination port for mirrored traffic Mirror enable
Data Sheet
Bit [6:4]: Bit [7]:
12.3.9 12.3.9.1
(Group 8 Address) Per Port QOS Control FCRn - Port 0~3,8,9 Flooding Control Register
IC Address h04C-055; CPU Address:h800+N (N = port number) Accessed by CPU and IC (R/W) Bit [3:0]: U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits [6:4]. This is used to limit the amount of flooding traffic from Port N. The value in U2MR specifies how many packets are allowed to flood within the time specified by bit [6:4]. To disable this function, program U2MR to 0. (Default = 0) Time Base for Unicast to Multicast, Multicast and Broadcast rate control of Port N: (Default = 000) 000 = 100us 001 = 200us 010 = 400us 011 = 800us 100 = 1.6ms 101 = 3.2ms 110 = 6.4ms 111 = 12.8ms Reserved
Bit [6:4]:
Bit [7]:
12.3.9.2
BMRCn - Port 0~3,8,9 Broadcast/Multicast Rate Control
IC Address h05E-067, CPU Address:h820+N (N = port number) Accessed by CPU and IC (R/W) This broadcast and multicast rate defines for Port N, the number of packets allowed to be forwarded within a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field to 0. Time base is based on register FCR0 [6:4].
84
Zarlink Semiconductor Inc.
ZL50404
Bit [3:0]: Bit [7:4]:
Data Sheet
Multicast Rate Control. Number of multicast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCRn). (Default 0). Broadcast Rate Control. Number of broadcast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCRn). (Default 0)
12.3.9.3
PR100_n - Port 0~3 Reservation
IC Address h06A-06D, CPU Address 840+N (N = port number) Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.4
PR100_CPU - Port CPU Reservation
IC Address h073, CPU Address 848 Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.5
PRM - Port MMAC Reservation
IC Address h072, CPU Address 849 Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. (Default 0x24)
12.3.9.6
PTH100_n - Port 0~3 Threshold
IC Address h0C2-0C5, CPU Address 860+N (N = port number) Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger ether random drop or flow control (Default 0x3)
12.3.9.7
PTH100_CPU - Port CPU Threshold
IC Address h0CB, CPU Address 868 Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger ether random drop or flow control (Default 0x3)
12.3.9.8
PTHM - Port MMAC Threshold
IC Address h0CA, CPU Address 869 Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger ether random drop or flow control (Default 0x12)
85
Zarlink Semiconductor Inc.
ZL50404
12.3.9.9
* *
Data Sheet
QOSC00, QOSC01 - Classes Byte Limit port 0
Accessed by CPU and IC (R/W) QOSC00 - BYTE_L1 (IC Address h078, CPU Address 880) QOSC01 - BYTE_L2 (IC Address h079, CPU Address 881)
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the queue size exceeds L2 threshold, received frame will ether be filtered (high drop) or subject to Z% WRED.
12.3.9.10
QOSC02, QOSC07 - Classes Byte Limit port 1-3
IC Address 07A-07F, CPU Address:h882-887 Accessed by CPU and IC (R/W) Same as QOSC00, QOSC01
12.3.9.11
* * * * * * QOSC16 QOSC17 QOSC18 QOSC19 QOSC20 QOSC21
QOSC16 - QOSC21 - Classes Byte Limit CPU port
- - - - - - BYTE_L11 Level 1 for queue 1 (CPU Address 890) BYTE_L21 Level 2 for queue 1 (CPU Address 891) BYTE_L12 Level 1 for queue 2 (CPU Address 892) BYTE_L22 Level 2 for queue 2 (CPU Address 893) BYTE_L13 Level 1 for queue 3 (CPU Address 894) BYTE_L23 Level 2 for queue 3 (CPU Address 895)
Accessed by CPU (R/W):
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the queue size exceeds L2 threshold, received frame will ether be filtered (high drop) or subject to Z% WRED.
12.3.9.12
* * * * * * QOSC22 QOSC23 QOSC24 QOSC25 QOSC26 QOSC27
QOSC22 - QOSC27 - Classes Byte Limit MMAC port
- - - - - - BYTE_L11 Level 1 for queue 1 (IC Address h088, CPU Address 896) BYTE_L21 Level 2 for queue 1 (IC Address h089, CPU Address 897) BYTE_L12 Level 1 for queue 2 (IC Address h08A, CPU Address 898) BYTE_L22 Level 2 for queue 2 (IC Address h08B, CPU Address 899) BYTE_L13 Level 1 for queue 3 (IC Address h08C, CPU Address 89A) BYTE_L23 Level 2 for queue 3 (IC Address h08D, CPU Address 89B)
Accessed by CPU and IC (R/W)
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the queue size exceeds L2 threshold, received frame will ether be filtered (high drop) or subject to Z% WRED.
12.3.9.13
* * * * W3 W2 W1 W0 - - - -
QOSC28 - QOSC31 - Classes WFQ Credit For MMAC
- - - - CREDIT_C00 CREDIT_C01 CREDIT_C02 CREDIT_C03 (CPU (CPU (CPU (CPU Address Address Address Address 89C) 89D) 89E) 89F)
Accessed by CPU (R/W) QOSC28[5:0] QOSC29[5:0] QOSC30[5:0] QOSC31[5:0]
86
Zarlink Semiconductor Inc.
ZL50404
Data Sheet
QOSC28 through QOSC31 represents one set of WFQ parameters for MMAC port. The granularity of the numbers is 1, and their sum must be 64. QOSC31 corresponds to W0 that is the highest priority, and QOSC27 corresponds to W3. Default scheduling method will be strict priority across all queues. Only when the bit 7 in the class is set, the queue will be scheduled as WFQ. The credit number also works as shaper credit if bit 6 is set. The queue with shaper enabled will be scheduled by strict priority when the token is available. The shaper setting override the NS setting. Bit [5:0]: Bit [6]: Bit [7]: Class scheduling credit Shaper enable Not strict priority apply
12.3.9.14
* * * * W3 W2 W1 W0 - - - -
QOSC36 - QOSC39 - Shaper Control Port MMAC
- - - - TOKEN_LIMIT_C00 TOKEN_LIMIT_C01 TOKEN_LIMIT_C02 TOKEN_LIMIT_C03 (CPU (CPU (CPU (CPU Address Address Address Address 8A4) 8A5) 8A6) 8A7)
Accessed by CPU (R/W) QOSC36[7:0] QOSC37[7:0] QOSC38[7:0] QOSC39[7:0]
QOSC36 through QOSC39 represents one set of token limit on the shaper of MMAC port. The granularity of the numbers is 64 bytes. The shaper is implemented as leaky bucket and the limit here works as bucket size. Since the hardware implementation can keep negative number, the limit can be as small as one and still can transmit oversized frame, as long as one byte token is available.
12.3.10
(Group E Address) System Diagnostic
NOTE: Device Manufacturing test registers.
12.3.10.1 DTSRL - Test Output Selection
CPU Address E00 Accessed by CPU (R/W) Test group selection for testout[7:0].
12.3.10.2
DTSRM - Test Output Selection
CPU Address E01 Accessed by CPU (R/W) Test group selection for testout[15:8].
12.3.10.3
TESTOUT0, TESTOUT1 - Testmux Output [7:0], [15:8]
CPU Address E02, E03 Accessed by CPU (RO)
87
Zarlink Semiconductor Inc.
ZL50404
12.3.10.4 MASK0-MASK4 - Timeout Reset Mask
CPU Address E10-E14 Accessed by CPU (R/W) Disable timeout reset on selected state machine status.
Data Sheet
12.3.10.5
BOOTSTRAP0 - BOOTSTRAP2
CPU Address E80-E82 Accessed by CPU (RO) 23 BT2 Bit [15:0]: 15 BT1 BT0 0
Bootstrap value from TSTOUT[15:0]: Bit [6:0]: TSTOUT[6:0] Bit [8:7]: Invert of TSTOUT[8:7] Bit [9]: TSTOUT[11] Bit [10]: TSTOUT[9] Bit [11]: TSTOUT[10] Bit [14:12]: TSTOUT[14:12] Bit [15]: Always 0 Bootstrap value from M[3:0]_TXEN Bit [16]: M0_TXEN ... Bit [19]: M3_TXEN Reserved
Bit [19:16]:
Bit [23:20]:
12.3.10.6
PRTFSMST[9,8,3:0]
CPU Address E90-E99 Accessed by CPU (RO) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: TX FSM NOT idle for 5 sec TX FIFO control NOT idle for 5 sec RX SFD detection NOT idle for 5 sec RXINF NOT idle for 5 sec PTCTL NOT idle for 5 sec Reserved LHB frame detected LHB receiving timeout
88
Zarlink Semiconductor Inc.
ZL50404
12.3.10.7 PRTQOSST0-PRTQOSST3
CPU Address EA0 - EA3 Accessed by CPU (RO) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Source port reservation low No source port buffer left Unicast congestion detected on best effort queue Reserved High priority queue reach L1 WRED level High priority queue reach L2 WRED level Low priority MC queue full High priority MC queue full
Data Sheet
12.3.10.8
PRTQOSST8A, PRTQOSST8B (CPU port)
CPU Address EA8 - EA9 Accessed by CPU (RO) 15 PQSTB Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Bit [8]: Bit [9]: Bit [10]: Bit [11]: Bit [12]: Bit [13]: Bit [15:14]: Source port reservation low No source port buffer left Unicast congestion detected on best effort queue Reserved priority queue 1 reach L1 WRED level priority queue 1 reach L2 WRED level priority queue 2 reach L1 WRED level priority queue 2 reach L2 WRED level priority queue 3 reach L1 WRED level priority queue 3 reach L2 WRED level priority 0 MC queue full priority 1 MC queue full priority 2 MC queue full Priority 3 MC queue full Reserved PQSTA 0
89
Zarlink Semiconductor Inc.
ZL50404
12.3.10.9 PRTQOSST9A, PRTQOSST9B (MMAC port)
CPU Address EAA - EAB Accessed by CPU (RO) 15 PQSTB Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Bit [8]: Bit [9]: Bit [10]: Bit [11]: Bit [12]: Bit [13]: Bit [15:14]: Source port reservation low No source port buffer left Unicast congestion detected on best effort queue Reserved Priority queue 1 reach L1 WRED level Priority queue 1 reach L2 WRED level Priority queue 2 reach L1 WRED level Priority queue 2 reach L2 WRED level Priority queue 3 reach L1 WRED level Priority queue 3 reach L2 WRED level Priority 0 MC queue full Priority 1 MC queue full Priority 2 MC queue full Priority 3 MC queue full Reserved PQSTA 0
Data Sheet
12.3.10.10
CLASSQOSST
CPU Address EAC Accessed by CPU (RO) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [7:4]: No share buffer No class 1 buffer No class 2 buffer No class 3 buffer Reserved
90
Zarlink Semiconductor Inc.
ZL50404
12.3.10.11 PRTINTCTR
CPU Address EAD Accessed by CPU (R/W) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Interrupt when source buffer low Interrupt when no source buffer Interrupt when UC congest Interrupt when L1 WRED level Interrupt when L2 WRED level Interrupt when MC queue full Interrupt when LHB timeout Interrupt when no class buffer
Data Sheet
12.3.10.12
QMCTRL[9,8,3:0]
CPU Address EB0 - EB9 Accessed by CPU (R/W) Bit [0]: Bit [1]: Bit [4:2]: Bit [5]: Bit [6]: Bit [7]: Suspend port scheduling (no departure) Reset queue Reserved Force out MAC control frame Force out XOFF flow control frame Force out XON flow control frame
12.3.10.13
QCTRL
CPU Address EBA Accessed by CPU (R/W) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [7:4]: Stop QM FSM at idle Stop MCQ FSM at idle Stop new granule grant to any source Stop release granule from any source Reserved
91
Zarlink Semiconductor Inc.
ZL50404
12.3.10.14 BMBISTR0, BMBISTR1
CPU Address EBB, EBC Accessed by CPU (RO)
Data Sheet
12.3.10.15
BMControl
CPU Address EBD Accessed by CPU (R/W) Bit [3:0]: Block Memory redundancy control 0: Use hardware detected value All others: Overwrite the hardware detected memory swap map Reserved
Bit [7:4]:
12.3.10.16
BUFF_RST
CPU Address EC0 Accessed by CPU (R/W) Bit [3:0] Assign a value that the pool to be reset 0: port 0 pool 1: port 1 pool 2: port 2 pool 3: port 3 pool 4-7: reserved 8: port MMAC pool 9: shared pool 10: class 1 pool 11: class 2 pool 12: class 3 pool 13: multicast pool 14: cpu pool 15: reserved If this bit is 1, then all the pools are assigned Set 1 to reset the pools that are assigned Reserved
Bit [4] Bit [5] Bit [7:6]
If CPU wants to reset pools again, CPU has to clear bit 5 and then set bit 5. Note: Before CPU doing so, CPU should set QCTRL (CPU Address EBA) bit 2 and bit 3 to one. After reset the pools, CPU shall reprogram free granule link list (CPU address EC1, EC2, EC3, EC4, EC5, EC6). Then clear QCTRL (EBA).
92
Zarlink Semiconductor Inc.
ZL50404
12.3.10.17 FCB_HEAD_PTR0, FCB_HEAD_PTR1
CPU address EC1 Accessed by CPU (R/W) Bit [7:0] Fcb_head_ptr[7:0]. The head pointer of free granule link that CPU assigns.
Data Sheet
CPU address EC2 Accessed by CPU (R/W) Bit [6:0] Bit [7] Fcb_head_ptr[14:8]. The head pointer of free granule link that CPU assigns. Set 1 to write
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15.
12.3.10.18
FCB_TAIL_PTR0, FCB_TAIL_PTR1
CPU address EC3 Accessed by CPU (R/W) Bit [7:0] Fcb_tail_ptr[7:0]. The tail pointer of free granule link that CPU assigns.
CPU address EC4 Accessed by CPU (R/W) Bit [6:0] Bit [7] Fcb_tail_ptr[14:8]. The tail pointer of free granule link that CPU assigns. Set 1 to write
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15.
12.3.10.19
FCB_NUM0, FCB_NUM1
CPU address EC5 Accessed by CPU (R/W) Bit [7:0] Fcb_number[7:0]. The total number of granules that CPU assigns.
CPU address EC6 Accessed by CPU (R/W) Bit [6:0] Bit [7] Fcb_number[14:8]. The total number of granules that CPU assigns. Set 1 to write
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15.
93
Zarlink Semiconductor Inc.
ZL50404
Note: There are two ways to reprogram the free granules.
Data Sheet
1. CPU links all the granules: CPU writes memory directly, at last write head pointer (address EC1, EC2), tail pointer (address EC3, EC4) and granule number (address EC5, EC6). 2. CPU tells Buffer Manager to link: CPU clear head pointer (address EC1, EC2), clear tail pointer (address EC3, EC4), then write granule number that tells Buffer Manager to link (address EC5, EC6).
12.3.10.20
BM_RLSFF_CTRL
CPU address EC7 Accessed by CPU (R/W) Bit [0] Bit [7:1] Read BM release FIFO. Reserved
The information of BM release FIFO is relocated to registers BM_RLSFF_INFO (address ECD, ECC, ECB, ECA, EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit 0 is changing from 0 to 1.
12.3.10.21
BM_RSLFF_INFO[5:0]
CPU address EC8 Accessed by CPU (RO) Bit [7:0] Rls_head_ptr[7:0].
CPU address EC9 Accessed by CPU (RO) Bit [6:0] Bit [7] Rls_head_ptr[14:8]. Rls_tail_ptr[0]
CPU address ECA Accessed by CPU (RO) Bit [7:0] Rls_tail_ptr[8:1]
CPU address ECB Accessed by CPU (RO) Bit [5:0] Bit [7:6] Rls_tail_ptr[14:9] Rls_count[1:0]
94
Zarlink Semiconductor Inc.
ZL50404
CPU address ECC Accessed by CPU (RO) Bit [4:0] Bit [5] Bit [7:6] Rls_count[6:2] If 1, then It is multicast packet. Rls_src_port[1:0[
Data Sheet
CPU address ECD Accessed by CPU (RO) Bit [1:0] Bit [3:2] Bit [4] Bit [7:5] Rls_src_port[3:2] Class[1:0] This release request is from QM directly. Entries count in release FIFO, 0 means FIFO is empty
12.3.11 12.3.11.1
(Group F Address) CPU Access Group GCR - Global Control Register
CPU Address: hF00 Accessed by CPU (R/W) Bit [0]: Bit[1]: Bit[2]: Bit[3]: Bit[4]: Store configuration (Default = 0) Write `1' followed by `0' to store configuration into external EEPROM Store configuration and reset (Default = 0) Write `1' to store configuration into external EEPROM and reset chip Start BIST (Default = 0) Write `1' followed by `0' to start the device's built-in self-test. The result is found in the DCR register. Soft Reset (Default = 0) Write `1' to reset chip Initialization Completed (Default = 0) This bit is reserved in unmanaged mode. In managed mode, the CPU writes this bit with `1' to indicate initialization is completed and ready to forward packets. The '0' to '1' transition will toggle TSTOUT[2] from low to high. Reserved
Bit[7:5]:
95
Zarlink Semiconductor Inc.
ZL50404
12.3.11.2 DCR - Device Status and Signature Register
CPU Address: hF01 Accessed by CPU (RO) Bit [0]: Bit[1]: Bit[2]: Bit[3]: Bit[5:4]: Bit [7:6]: 1: Busy writing configuration to IC 0: Not busy (not writing configuration to IC) 1: Busy reading configuration from IC 0: Not busy (not reading configuration from IC) 1: BIST in progress 0: BIST not running 1: RAM Error 0: RAM OK Device Signature 10: ZL50404 device Revision 00: Initial Silicon 01: Second Silicon
Data Sheet
12.3.11.3
DCR1 - Device Status Register 1
CPU Address: hF02 Accessed by CPU (RO) Bit [6:0] Bit [7] Reserved Chip initialization completed
12.3.11.4
DPST - Device Port Status Register
CPU Address:hF03 Accessed by CPU (R/W) Bit[4:0]: Read back index register. This is used for selecting what to read back from DTST. (Default 00) 5'b00000 - Port 0 Operating mode and Negotiation status 5'b00001 - Port 1 Operating mode and Negotiation status 5'b00010 - Port 2 Operating mode and Negotiation status 5'b00011 - Port 3 Operating mode and Negotiation status 5'b001XX - Reserved 5'b01000 - Port CPU Operating mode and Negotiation status 5'b01001 - Port MMAC Operating mode and Negotiation status Reserved
Bit[7:5]:
96
Zarlink Semiconductor Inc.
ZL50404
12.3.11.5 DTST - Data read back register
CPU Address: hF04 Accessed by CPU (RO)
Data Sheet
This register provides various internal information as selected in DPST bit[4:0]. Refer to the PHY Control Application Note. Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Flow control enable Full duplex port Fast Ethernet port Link is down Auto negotiation enabled 1: Disable 0: Enable Reserved Module detected (for hot swap purpose)
Bit[5:6] Bit[7]
12.3.11.6
DA - DA Register
CPU Address: hFFF Accessed by CPU (RO) Always return 8'h DA. Indicate the CPU interface or serial port connection is good. Bit[7:0] Always return DA
97
Zarlink Semiconductor Inc.
ZL50404
13.0
13.1
Data Sheet
Characteristics and Timing
Absolute Maximum Ratings
-65C to +150C -40C to +85C +3.0 V to +3.6 V +1.70 V to +2.00 V -0.5 V to (VCC + 2.5 V) -0.5 V to (VDD + 0.3 V)
Storage Temperature Operating Temperature Supply Voltage VCC with Respect to VSS Supply Voltage VDD with Respect to VSS Voltage on 5V Tolerant Input Pins Voltage on Other Pins
Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied.
13.2
DC Electrical Characteristics
TAMBIENT = -40 C to +85 C
VCC = 3.0 V to 3.6 V (3.3v +/- 10%) VDD = 1.8V +5% - 5%
98
Zarlink Semiconductor Inc.
ZL50404
13.3 Recommended Operation Conditions
Data Sheet
Recommended Operation Conditions Symbol fosc ICC IDD VOH VOL VIH VIL IIL Parameter Description Frequency of Operation VCC Supply Current - @ 25 MHz VDD Supply Current - @ 25 MHz Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5V tolerant) Input Low Voltage (TTL 5V tolerant) Input Leakage Current (0.1 V < VIN < VCC) (all pins except those with internal pull-up/pull-down resistors) Output Leakage Current (0.1 V < VOUT < VCC) Input Capacitance Output Capacitance I/O Capacitance Thermal resistance with 0 air flow Thermal resistance with 1 m/s air flow Thermal resistance with 2m/s air flow Thermal resistance between junction and case VCC x 70% VCC - 0.5 0.5 VCC + 2.0 VCC x 30% 10 Min Typ 25 45 160 Max Unit MHz mA mA V V V V A
IOL CIN COUT CI/O ja ja ja jc
10 5 5 7 24.3 20.0 18.1 4.6
A pF pF pF C/W C/W C/W C/W
99
Zarlink Semiconductor Inc.
ZL50404
13.4 13.4.1 AC Characteristics and Timing Typical Reset & Bootstrap Timing Diagram
Data Sheet
RESIN#
RESETOUT# Tri-Stated
R1 R3
Bootstrap Pins Outputs Inputs
R2
Outputs
Figure 10 - Typical Reset & Bootstrap Timing Diagram
Symbol R1 R2 R3
Parameter Delay until RESETOUT# is tri-stated Bootstrap stabilization RESETOUT# assertion
Min
Typ 10ns
Note: RESETOUT# state is then determined by the external pull-up/down resistor Bootstrap pins sampled on rising edge of RESIN#
1s
10s 2ms
100
Zarlink Semiconductor Inc.
ZL50404
13.4.2 Reduced Media Independent Interface
M_CLK
M6-max M6-min
Data Sheet
M[3:0]_TXEN
M[3:0] _TXD[1:0]
M7-max M7-min
Figure 11 - AC Characteristics - Reduced media independent Interface (TX)
M_CLK
M2 M3 M4 M5
M[3:0]_RXD M[3:0]_CRS_DV
Figure 12 - AC Characteristics - Reduced Media Independent Interface (RX)
50MHz Symbol M2 M3 M4 M5 M6 M7 Parameter Min (ns) M[3:0]_RXD[1:0] Input Setup Time M[3:0]_RXD[1:0] Input Hold Time M[3:0]_CRS_DV Input Setup Time M[3:0]_CRS_DV Input Hold Time M[3:0]_TXEN Output Delay Time M[3:0]_TXD[1:0] Output Delay Time 4 2 4 3 2 2 11 11 CL = 20 pF CL = 20 pF Max (ns) Note:
101
Zarlink Semiconductor Inc.
ZL50404
13.4.3 Media Independent Interface
M[9:0] TXCLK
MM6-max MM6-min
Data Sheet
M[9:0]_TXEN
M[9:0] _TXD[3:0]
MM7-max MM7-min
Figure 13 - AC Characteristics - Media independent Interface (TX)
M[9:0]RXCLK
MM2 MM3 MM4 MM5
M[9:0]RXD[3:0] M[9:0]_CRS_DV
Figure 14 - AC Characteristics - Media Independent Interface (RX)
-25MHz Symbol MM2 MM3 MM4 MM5 MM6 MM7 Parameter Min (ns) M[9:0]_RXD[3:0] Input Setup Time M[9:0]_RXD[3:0] Input Hold Time M[9:0]_CRS_DV Input Setup Time M[9:0]_CRS_DV Input Hold Time M[9:0]_TXEN Output Delay Time M[9:0]_TXD[3:0] Output Delay Time 4 2 4 2 2 2 14 14 CL = 20 pF CL = 20 pF Max (ns) Note:
102
Zarlink Semiconductor Inc.
ZL50404
13.4.4 General Purpose Serial Interface (7-wire)
M[3:0] TXCLK
SM6-max SM6-min
Data Sheet
M[3:0]_TXEN
M[3:0] _TXD
SM7-max SM7-min
Figure 15 - AC Characteristics - General Purpose Serial Interface (TX)
M[3:0]RXCLK
SM2 SM3 SM4 SM5
M[3:0]_RXD M[3:0]_CRS_DV
Figure 16 - AC Characteristics - General Purpose Serial Interface (RX)
-10MHz Symbol SM2 SM3 SM4 SM5 SM6 SM7 Parameter Min (ns) M[3:0]_RXD Input Setup Time M[3:0]_RXD Input Hold Time M[3:0]_CRS_DV Input Setup Time M[3:0]_CRS_DV Input Hold Time M[3:0]_TXEN Output Delay Time M[3:0]_TXD Output Delay Time 4 2 4 2 2 2 14 14 CL = 20 pF CL = 20 pF Max (ns) Note:
Table 11 - AC Characteristics -General Purpose Serial Interface
103
Zarlink Semiconductor Inc.
ZL50404
13.4.5 MDIO Input Setup and Hold Timing
MDC
D1 D2
Data Sheet
MDIO
Figure 17 - MDIO Input Setup and Hold Timing
MDC
D3-max D3-min
MDIO
Figure 18 - MDIO Output Delay Timing
500KHz Symbol D1 D2 D3 Parameter Min (ns) MDIO input setup time MDIO input hold time MDIO output delay time 10 2 1 20 CL = 50pf Max (ns) Note:
104
Zarlink Semiconductor Inc.
ZL50404
13.4.6 IC Input Setup Timing
SCL
S1 S2
Data Sheet
SDA
Figure 19 - IC Input Setup Timing
SCL
S3-max S3-min
SDA
Figure 20 - IC Output Delay Timing
50KHz Symbol S1 S2 S3* Parameter Min (ns) SDA input setup time SDA input hold time SDA output delay time 20 1 4 usec 6 usec CL = 30pf Max (ns) Note:
* Open Drain Output. Low to High transistor is controlled by external pullup resistor.
105
Zarlink Semiconductor Inc.
ZL50404
13.4.7 Serial Interface Setup Timing
Data Sheet
STROBE Datain D1 D2
D4 D1 D2
D5
Figure 21 - Serial Interface Setup Timing
STROBE
D3-max D3-min
Dataout
Figure 22 - Serial Interface Output Delay Timing
Symbol D1 D2 D2 D3 D4 D4 D5 D5 Datain setup time Datain hold time Datain hold time
Parameter
Min (ns) 20 3s 20ns 1 5s 50ns 5s 50ns
Max (ns)
Note:
Debounce on Debounce off 50 CL = 100pf Debounce on Debounce off Debounce on Debounce off
Dataout output delay time Strobe low time Strobe low time Strobe high time Strobe high time
106
Zarlink Semiconductor Inc.
ZL50404
13.4.8 JTAG (IEEE 1149.1-2001)
Data Sheet
TCK
TMS, TDI
J1
J2
J3-max
TDO
J3-min
Figure 23 - JTAG Timing Diagram
Symbol
Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time
Min 0 20 10 20 3 7 0
Typ 10
Max 50
Units MHz ns ns
Note:
-
ns ns ns
TRST is an asynchronous signal
J1 J2 J3
TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid
15
ns
107
Zarlink Semiconductor Inc.
TOP VIEW
BOTTOM VIEW
MIN MAX Dimension 1.40 A A1 0.30 0.50 0.53 REF A2 D 16.90 17.10 16.90 17.10 E 0.40 0.60 b 1.00 e N 208 Conforms to JEDEC MO-192
b
SIDE VIEW
c Zarlink Semiconductor 2002 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1 213730 14Nov02
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of ZL50404

	To Download ZL50404 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .